公开(公告)号：US20210073042A1

公开(公告)日：2021-03-11

申请号：US16562367

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/50 ,  G06F9/38 ,  G06F1/04 ,  G06F1/3296

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20210073125A1

公开(公告)日：2021-03-11

申请号：US16562361

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F12/06

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20210073025A1

公开(公告)日：2021-03-11

申请号：US16562359

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, JR. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/48 ,  G06F9/46 ,  G06T1/20

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20230297485A1

公开(公告)日：2023-09-21

申请号：US17698668

申请日：2022-03-18

Applicant: NVIDIA CORPORATION

Inventor： Pranav VAIDYA ,  Alan MENEZES ,  Siddharth SHARMA ,  Jin OUYANG ,  Gregory Paul SMITH ,  Timothy J. MCDONALD ,  Shounak KAMALAPURKAR ,  Abhijat RANADE ,  Thomas Melvin OGLETREE

IPC: G06F11/34 ,  G06F21/60 ,  G06F1/10

CPC classification number: G06F11/3409 ,  G06F21/602 ,  G06F1/10

Abstract: Various embodiments include a system for generating performance monitoring data in a computing system. The system includes a unit level counter with a set of counters, where each counter increments during each clock cycle in which a corresponding electronic signal is at a first state, such as a high or low logic level state. Periodically, the unit level counter transmits the counter values to a corresponding counter collection unit. The counter collection unit includes a set of counters that aggregates the values of the counters in multiple unit level counters. Based on certain trigger conditions, the counter collection unit transmits records to a reduction channel. The reduction channel includes a set of counters that aggregates the values of the counters in multiple counter collection units. Each virtual machine executing on the system can access a different corresponding reduction channel, providing secure performance metric data for each virtual machine.

公开(公告)号：US20210157651A1

公开(公告)日：2021-05-27

申请号：US17164718

申请日：2021-02-01

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsay EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/455 ,  G06F9/48

Abstract: A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20210073035A1

公开(公告)日：2021-03-11

申请号：US16562364

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. DULUK, Jr. ,  Gregory Scott PALMER ,  Jonathon Stuart Ramsey EVANS ,  Shailendra SINGH ,  Samuel H. DUNCAN ,  Wishwesh Anil GANDHI ,  Lacky V. SHAH ,  Eric ROCK ,  Feiqi SU ,  James Leroy DEMING ,  Alan MENEZES ,  Pranav VAIDYA ,  Praveen JOGINIPALLY ,  Timothy John PURCELL ,  Manas MANDAL

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/38

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.