公开(公告)号：US20230289211A1

公开(公告)日：2023-09-14

申请号：US17691872

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Gentaro HIROTA ,  Tanmoy MANDAL ,  Jeff TUCKEY ,  Kevin STEPHANO ,  Chen MEI ,  Shayani DEB ,  Naman GOVIL ,  Rajballav DASH ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4843 ,  G06F9/505

Abstract: A processor supports new thread group hierarchies by centralizing work distribution to provide hardware-guaranteed concurrent execution of thread groups in a thread group array through speculative launch and load balancing across processing cores. Efficiencies are realized by distributing grid rasterization among the processing cores.

公开(公告)号：US20230236878A1

公开(公告)日：2023-07-27

申请号：US17583957

申请日：2022-01-25

Applicant: NVIDIA CORPORATION

Inventor： Jack Hilaire CHOQUETTE ,  Rajballav DASH ,  Shayani DEB ,  Gentaro HIROTA ,  Ronny M. KRASHINSKY ,  Ze LONG ,  Chen MEI ,  Manan PATEL ,  Ming Y. SIU

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: In various embodiments, scheduling dependencies associated with tasks executed on a processor are decoupled from data dependencies associated with the tasks. Before the completion of a first task that is executing in the processor, a scheduling dependency specifying that a second task is dependent on the first task is resolved based on a pre-exit trigger. In response to the resolution of the scheduling dependency, the second task is launched on the processor.