公开(公告)号：US20250078199A1

公开(公告)日：2025-03-06

申请号：US18239733

申请日：2023-08-29

Applicant: NVIDIA Corporation

Inventor： Wish GANDHI ,  Ze LONG ,  Kun FANG

IPC: G06T1/60

Abstract: A GPU can selectively confine software function execution and associated data storage resources to locally-connected processing/storage components, thereby minimizing latency and other overhead that would otherwise be needed to access more remote resources. The GPU can selectively permit other software function execution and associated data storage resources to range across non-locally-connected processing/storage components when more processing and/or storage resources are required.

公开(公告)号：US20230289211A1

公开(公告)日：2023-09-14

申请号：US17691872

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Gentaro HIROTA ,  Tanmoy MANDAL ,  Jeff TUCKEY ,  Kevin STEPHANO ,  Chen MEI ,  Shayani DEB ,  Naman GOVIL ,  Rajballav DASH ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4843 ,  G06F9/505

Abstract: A processor supports new thread group hierarchies by centralizing work distribution to provide hardware-guaranteed concurrent execution of thread groups in a thread group array through speculative launch and load balancing across processing cores. Efficiencies are realized by distributing grid rasterization among the processing cores.

公开(公告)号：US20230289215A1

公开(公告)日：2023-09-14

申请号：US17691621

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Greg PALMER ,  Gentaro HIROTA ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS ,  Rajballav DASH ,  Jeff TUCKEY ,  Jerome F. DULUK, JR. ,  Lacky SHAH ,  Luke DURANT ,  Jack CHOQUETTE ,  Eric WERNESS ,  Naman GOVIL ,  Manan PATEL ,  Shayani DEB ,  Sandeep NAVADA ,  John EDMONDSON ,  Prakash BANGALORE PRABHAKAR ,  Wish GANDHI ,  Ravi MANYAM ,  Apoorv PARLE ,  Olivier GIROUX ,  Shirish GADRE ,  Steve HEINRICH

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/3851 ,  G06F9/3009 ,  G06F9/544

Abstract: A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

公开(公告)号：US20230236878A1

公开(公告)日：2023-07-27

申请号：US17583957

申请日：2022-01-25

Applicant: NVIDIA CORPORATION

Inventor： Jack Hilaire CHOQUETTE ,  Rajballav DASH ,  Shayani DEB ,  Gentaro HIROTA ,  Ronny M. KRASHINSKY ,  Ze LONG ,  Chen MEI ,  Manan PATEL ,  Ming Y. SIU

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: In various embodiments, scheduling dependencies associated with tasks executed on a processor are decoupled from data dependencies associated with the tasks. Before the completion of a first task that is executing in the processor, a scheduling dependency specifying that a second task is dependent on the first task is resolved based on a pre-exit trigger. In response to the resolution of the scheduling dependency, the second task is launched on the processor.

公开(公告)号：US20230289189A1

公开(公告)日：2023-09-14

申请号：US17691690

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Prakash BANGALORE PRABHAKAR ,  Gentaro HIROTA ,  Ronny KRASHINSKY ,  Ze LONG ,  Brian PHARRIS ,  Rajballav DASH ,  Jeff TUCKEY ,  Jerome F. DULUK, JR. ,  Lacky SHAH ,  Luke DURANT ,  Jack CHOQUETTE ,  Eric WERNESS ,  Naman GOVIL ,  Manan PATEL ,  Shayani DEB ,  Sandeep NAVADA ,  John EDMONDSON ,  Greg PALMER ,  Wish GANDHI ,  Ravi MANYAM ,  Apoorv PARLE ,  Olivier GIROUX ,  Shirish GADRE ,  Steve HEINRICH

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

公开(公告)号：US20230021678A1

公开(公告)日：2023-01-26

申请号：US17380424

申请日：2021-07-20

Applicant: NVIDIA CORPORATION

Inventor： Michael Allen PARKER ,  Debajit BHATTACHARYA ,  David FONTAINE ,  Shirish GADRE ,  Wishwesh Anil GANDHI ,  Olivier GIROUX ,  Hemayet HOSSAIN ,  Ronny M. KRASHINSKY ,  Ze LONG ,  Raymond Hoi Man WONG

IPC: G06F9/52 ,  G06F9/30

Abstract: Various embodiments include a parallel processing computer system that provides multiple memory synchronization domains in a single parallel processor to reduce unneeded synchronization operations. During execution, one execution kernel may synchronize with one or more other execution kernels by processing outstanding memory references. The parallel processor tracks memory references for each domain to each portion of local and remote memory. During synchronization, the processor synchronizes the memory references for a specific domain while refraining from synchronizing memory references for other domains. As a result, synchronization operations between kernels complete in a reduced amount of time relative to prior approaches.