Surface resource view hash for coherent cache operations in texture processing hardware
    1.
    发明授权
    Surface resource view hash for coherent cache operations in texture processing hardware 有权
    用于纹理处理硬件中相干缓存操作的表面资源视图散列

    公开(公告)号:US09448935B2

    公开(公告)日:2016-09-20

    申请号:US14037212

    申请日:2013-09-25

    Abstract: Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.

    Abstract translation: 公开了用于执行存储器访问操作的技术。 纹理单元接收包括与多个视图中的第一视图相关联的元组的存储器访问操作。 纹理单元检索与多个纹理标题中的第一纹理标题相关联的第一散列值,其中第一纹理标题与第一视图相关。 纹理单元检索与多个纹理标题中的第二纹理标题相关联的第二散列值,其中第二纹理标题与第二视图相关。 基于第一和第二哈希值,纹理单元确定第一视图是否与第二视图潜在地别名。 如果是,则纹理单元使与第二纹理头相关联的高速缓冲存储器中的高速缓存条目无效。 否则,纹理单元维护高速缓存条目。

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