公开(公告)号：US11907717B2

公开(公告)日：2024-02-20

申请号：US18107374

申请日：2023-02-08

Applicant: NVIDIA Corporation

Inventor： Andrew Kerr ,  Jack Choquette ,  Xiaogang Qiu ,  Omkar Paranjape ,  Poornachandra Rao ,  Shirish Gadre ,  Steven J. Heinrich ,  Manan Patel ,  Olivier Giroux ,  Alan Kaatz

IPC: G06F9/30 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0888

CPC classification number: G06F9/30043 ,  G06F9/3009 ,  G06F9/522 ,  G06F12/0808 ,  G06F12/0888 ,  G06F9/3004

Abstract: A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

公开(公告)号：US11604649B2

公开(公告)日：2023-03-14

申请号：US17363561

申请日：2021-06-30

Applicant: NVIDIA Corporation

Inventor： Andrew Kerr ,  Jack Choquette ,  Xiaogang Qiu ,  Omkar Paranjape ,  Poornachandra Rao ,  Shirish Gadre ,  Steven J. Heinrich ,  Manan Patel ,  Olivier Giroux ,  Alan Kaatz

IPC: G06F9/30 ,  G06F12/0808 ,  G06F12/0888 ,  G06F9/32 ,  G06F9/38 ,  G06F9/52 ,  G06F9/54

Abstract: A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

公开(公告)号：US20210124582A1

公开(公告)日：2021-04-29

申请号：US16712083

申请日：2019-12-12

Applicant: NVIDIA Corporation

Inventor： Andrew Kerr ,  Jack Choquette ,  Xiaogang Qiu ,  Omkar Paranjape ,  Poornachandra Rao ,  Shirish Gadre ,  Steven J. Heinrich ,  Manan Patel ,  Olivier Giroux ,  Alan Kaatz

IPC: G06F9/30 ,  G06F12/0888 ,  G06F12/0808

Abstract: A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

公开(公告)号：US20230185570A1

公开(公告)日：2023-06-15

申请号：US18107374

申请日：2023-02-08

Applicant: NVIDIA Corporation

Inventor： Andrew KERR ,  Jack Choquette ,  Xiaogang Qiu ,  Omkar Paranjape ,  Poornachandra Rao ,  Shirish Gadre ,  Steven J. Heinrich ,  Manan Patel ,  Olivier Giroux ,  Alan Kaatz

IPC: G06F9/30 ,  G06F12/0808 ,  G06F12/0888 ,  G06F9/32 ,  G06F9/38 ,  G06F9/52 ,  G06F9/54

CPC classification number: G06F9/30043 ,  G06F12/0808 ,  G06F12/0888 ,  G06F9/3009 ,  G06F9/321 ,  G06F9/3871 ,  G06F9/522 ,  G06F9/542 ,  G06F9/544 ,  G06F9/546 ,  G06F9/3838 ,  G06F2212/621 ,  G06F9/3004

Abstract: A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

公开(公告)号：US09595075B2

公开(公告)日：2017-03-14

申请号：US14038599

申请日：2013-09-26

Applicant: NVIDIA CORPORATION

Inventor： Steven J. Heinrich ,  Eric T. Anderson ,  Jeffrey A. Bolz ,  Jonathan Dunaisky ,  Ramesh Jandhyala ,  Joel McCormack ,  Alexander L. Minkin ,  Bryon S. Nordquist ,  Poornachandra Rao

IPC: G06T15/04 ,  G06T1/20 ,  G06T1/60 ,  G09G5/36

CPC classification number: G06T1/60 ,  G06F2212/302 ,  G06T1/20 ,  G06T15/04 ,  G09G5/363

Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

Abstract translation: 公开了用于在具有被配置为处理纹理存储器访问操作的第一部分的纹理处理流水线中执行存储器访问操作的方法和被配置为处理非纹理存储器访问操作的第二部分。 纹理单元接收存储器访问请求。 纹理单元确定存储器访问请求是否包括纹理存储器访问操作。 如果存储器访问请求包括纹理存储器访问操作，则纹理单元至少通过纹理处理流水线的第一部分来处理存储器访问请求，否则，纹理单元至少经由第二部分处理存储器访问请求 纹理处理流水线。 所公开方法的一个优点是可以将相同的处理和高速缓冲存储器用于纹理操作和对各种其他地址空间的加载/存储操作，导致减少的表面积和功率消耗。

公开(公告)号：US09448935B2

公开(公告)日：2016-09-20

申请号：US14037212

申请日：2013-09-25

Applicant: NVIDIA CORPORATION

Inventor： Jeff Bolz ,  Patrick R. Brown ,  Steven J. Heinrich ,  Dale L. Kirkland ,  Joel McCormack

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F12/0815 ,  G06F12/1018 ,  G06F12/128 ,  G06F2212/455 ,  Y02D10/13

Abstract: Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.

Abstract translation: 公开了用于执行存储器访问操作的技术。 纹理单元接收包括与多个视图中的第一视图相关联的元组的存储器访问操作。 纹理单元检索与多个纹理标题中的第一纹理标题相关联的第一散列值，其中第一纹理标题与第一视图相关。 纹理单元检索与多个纹理标题中的第二纹理标题相关联的第二散列值，其中第二纹理标题与第二视图相关。 基于第一和第二哈希值，纹理单元确定第一视图是否与第二视图潜在地别名。 如果是，则纹理单元使与第二纹理头相关联的高速缓冲存储器中的高速缓存条目无效。 否则，纹理单元维护高速缓存条目。

公开(公告)号：US11379944B2

公开(公告)日：2022-07-05

申请号：US16910029

申请日：2020-06-23

Applicant: NVIDIA CORPORATION

Inventor： Michael Fetterman ,  Shirish Gadre ,  Mark Gebhart ,  Steven J. Heinrich ,  Ramesh Jandhyala ,  William Newhall ,  Omkar Paranjape ,  Stefano Pescador ,  Poorna Rao

IPC: G06T1/20 ,  G06T1/60 ,  G06F16/245

Abstract: A texture processing pipeline in a graphics processing unit generates the surface appearance for objects in a computer-generated scene. This texture processing pipeline determines, at multiple stages within the texture processing pipeline, whether texture operations and texture loads may be processed at an accelerated rate. At each stage that includes a decision point, the texture processing pipeline assumes that the current texture operation or texture load can be accelerated unless specific, known information indicates that the texture operation or texture load cannot be accelerated. As a result, the texture processing pipeline increases the number of texture operations and texture loads that are accelerated relative to the number of texture operations and texture loads that are not accelerated.

公开(公告)号：US11080051B2

公开(公告)日：2021-08-03

申请号：US16712083

申请日：2019-12-12

Applicant: NVIDIA Corporation

Inventor： Andrew Kerr ,  Jack Choquette ,  Xiaogang Qiu ,  Omkar Paranjape ,  Poornachandra Rao ,  Shirish Gadre ,  Steven J. Heinrich ,  Manan Patel ,  Olivier Giroux ,  Alan Kaatz

IPC: G06F9/30 ,  G06F12/0808 ,  G06F12/0888

Abstract: A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.