公开(公告)号：US09542189B2

公开(公告)日：2017-01-10

申请号：US14046850

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Joseph Cavanaugh ,  Dale L. Kirkland ,  Emmett M. Kilgariff

IPC: G06F15/80 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/08 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.

Abstract translation: 本发明的一个实施例包括一种在基于瓦片的架构中处理图形基元的技术。 该技术包括在缓冲器中存储从世界空间流水线接收的第一多个图形基元和第一多个状态束，并将第一多个图形基元发送到屏幕空间管线以进行平铺功能 启用。 该技术还包括在缓冲器中存储从世界空间管道接收的第二多个图形基元和第二多个状态束。 该技术还包括基于第一条件来确定应该禁用平铺函数，并且应该从缓冲器刷新第二多个图形基元，并且将第二多个图形基元发送到屏幕空间管线用于处理 而平铺功能被禁用。