公开(公告)号：US10282803B2

公开(公告)日：2019-05-07

申请号：US14016789

申请日：2013-09-03

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Pierre Souillot ,  Cynthia Ann Edgeworth Allison ,  Dale L. Kirkland ,  Walter R. Steiner

IPC: G09G5/36 ,  G06T1/20 ,  G06T15/00 ,  G06T15/40 ,  G06F9/38 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/0808 ,  G06F12/0875 ,  G06F9/44 ,  G06T15/80 ,  G06T17/20

Abstract: One embodiment of the present invention includes a graphics subsystem that includes a tiling unit, a crossbar unit, and a screen-space pipeline. The crossbar unit is configured to transmit primitives interleaved with state change commands to the tiling unit. The tiling unit is configured to record an initial state associated with the primitives and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a first cache tile. The tiling unit is further configured to transmit the initial state to the screen-space pipeline and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a second cache tile. The tiling unit includes a state filter block configured to determine that a first state change in the state change commands is followed by a second state change, without an intervening primitive, and to forego transmitting the first state change in response.

公开(公告)号：US10083036B2

公开(公告)日：2018-09-25

申请号：US14045361

申请日：2013-10-03

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Dale L. Kirkland ,  Andrei Khodakovsky ,  Jeffrey A. Bolz

IPC: G09G5/36 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/0808 ,  G06F12/0875 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a technique for managing graphics processing resources in a tile-based architecture. The technique includes storing a release packet associated with a graphics processing resource in a buffer and initiating a replay of graphics primitives stored in the buffer and associated with the graphics processing resource. The technique further includes, for each tile included in a plurality of tiles and processed during the replay, reading the release packet and determining whether the tile is a last tile processed during the replay. The technique further includes determining not to transmit the release packet to a screen-space pipeline and continuing to read graphics data stored in the buffer if the tile is not the last tile to be processed during the replay, or transmitting the release packet to the screen-space pipeline if the tile is the last tile to be processed during the replay.

公开(公告)号：US09448804B2

公开(公告)日：2016-09-20

申请号：US14045367

申请日：2013-10-03

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Dale L. Kirkland

IPC: G09G5/36 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/08 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a technique for managing buffer entries in a tile-based architecture. The technique includes receiving a first plurality of graphics primitives and a first buffer address at which attributes associated with the first plurality of graphics primitives are stored. The technique further includes, for each tile included in a plurality of tiles, transmitting the first plurality of graphics primitives and the first buffer address to a screen space pipeline and receiving an acknowledgement from the screen space pipeline indicating that processing the first plurality of graphics primitives has completed. The technique further includes determining that processing the first plurality of graphics primitives has completed for a last tile included in the plurality of tiles and that the acknowledgement has been received for each tile included in the plurality of tiles, and, in response, releasing a buffer entry associated with the first buffer address.

Abstract translation: 本发明的一个实施例提出了一种用于在基于瓦片的架构中管理缓冲器条目的技术。 该技术包括接收第一多个图形基元和与第一多个图形基元相关联的属性被存储的第一缓冲器地址。 该技术还包括对于包括在多个瓦片中的每个瓦片，将第一多个图形基元和第一缓冲器地址传输到屏幕空间流水线并从屏幕空间流水线接收确认，指示处理第一多个图形基元 已经完成 该技术还包括确定第一多个图形基元对于包括在多个瓦片中的最后瓦片已经完成的处理，并且已经为包括在多个瓦片中的每个瓦片接收到该确认，并且作为响应，释放缓冲器 与第一个缓冲区地址相关联的条目。

公开(公告)号：US09792122B2

公开(公告)日：2017-10-17

申请号：US14046856

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Walter R. Steiner ,  Cynthia Ann Edgeworth Allison ,  Rouslan Dimitrov ,  Karim M. Abdalla ,  Dale L. Kirkland ,  Emmett M. Kilgariff

IPC: G06F9/38 ,  G06T15/80 ,  G06F9/44 ,  G06F12/08 ,  G06T15/50 ,  G09G5/395 ,  G09G5/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06F12/0808 ,  G06F12/0875

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.

公开(公告)号：US09639366B2

公开(公告)日：2017-05-02

申请号：US14045372

申请日：2013-10-03

Applicant: NVIDIA CORPORATION

Inventor： Karim M. Abdalla ,  Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Dale L. Kirkland

IPC: G09G5/36 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/0808 ,  G06F12/0875 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released.

公开(公告)号：US09542189B2

公开(公告)日：2017-01-10

申请号：US14046850

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Joseph Cavanaugh ,  Dale L. Kirkland ,  Emmett M. Kilgariff

IPC: G06F15/80 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/08 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.

Abstract translation: 本发明的一个实施例包括一种在基于瓦片的架构中处理图形基元的技术。 该技术包括在缓冲器中存储从世界空间流水线接收的第一多个图形基元和第一多个状态束，并将第一多个图形基元发送到屏幕空间管线以进行平铺功能 启用。 该技术还包括在缓冲器中存储从世界空间管道接收的第二多个图形基元和第二多个状态束。 该技术还包括基于第一条件来确定应该禁用平铺函数，并且应该从缓冲器刷新第二多个图形基元，并且将第二多个图形基元发送到屏幕空间管线用于处理 而平铺功能被禁用。

公开(公告)号：US10032243B2

公开(公告)日：2018-07-24

申请号：US14058053

申请日：2013-10-18

Applicant: NVIDIA Corporation

Inventor： Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Dale L. Kirkland ,  Walter R. Steiner

IPC: G06F15/16 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/00

Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed cache tiling. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.

公开(公告)号：US09483270B2

公开(公告)日：2016-11-01

申请号：US14058145

申请日：2013-10-18

Applicant: NVIDIA Corporation

Inventor： Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Dale L. Kirkland ,  Walter R. Steiner

IPC: G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/08 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed tiled caching. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.

Abstract translation: 本发明的一个实施例提出了一种被配置为实现分布式平铺高速缓存的图形子系统。 图形子系统包括一个或多个世界空间管道，一个或多个屏幕空间管道，一个或多个平铺单元和横梁单元。 每个世界空间流水线在不同的处理实体中实现，并且耦合到不同的平铺单元。 每个屏幕空间流水线在不同的处理实体中实现，并且耦合到交叉开关单元。 拼接单元被配置为从世界空间管道接收原语，基于图元生成高速缓存块批次，并将基元发送到屏幕空间管道。 所公开的方法的一个优点是在高度并行的平铺架构中以应用编程接口顺序处理原语。 另一个优点是以缓存平铺顺序处理图元，从而减少内存带宽消耗并提高高速缓存的使用率。