公开(公告)号：US20140281652A1

公开(公告)日：2014-09-18

申请号：US13831063

申请日：2013-03-14

Applicant: NVIDIA CORPORATION

Inventor： Tukaram Shankar Methar ,  Nilesh Acharya ,  Jyotirmaya Swain ,  Brian Lawrence Smith

IPC: H03L7/00 ,  G06F1/12

CPC classification number: H03L7/00 ,  G06F1/12

Abstract: A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first clock domain and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain. The synchronizer sub-unit includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers.

Abstract translation: 公开了一种包括用于跨异步边界同步数据的可选同步电路的系统和装置。 该设备包括与第一时钟域相关联的单元和耦合到该单元并与第二时钟域相关联的同步器子单元（SSU）。 同步器子单元包括两个或多个同步器和选择器逻辑，其被配置为选择两个或多个同步器的一个输出。

公开(公告)号：US20230057698A1

公开(公告)日：2023-02-23

申请号：US17409540

申请日：2021-08-23

Applicant: NVIDIA CORPORATION

Inventor： Jyotirmaya Swain ,  Padam KRISHNANI ,  Swapnil TAPADIA ,  Harshil JAIN

IPC: H04L29/06 ,  G06F12/06 ,  G06F13/40

Abstract: Various embodiments include techniques for processing transactions via a computer system interconnect with a distributed firewall. The distributed firewall includes separate firewalls for various initiators of transactions and separate firewalls for various targets of those transactions. As a result, transactions proceed, for example, along the shortest path from the initiator to the target, rather than being routed through a centralized firewall. In addition, firewall transactions, for example, may be remapped such that initiators address the initiator firewalls and target firewalls via a unified address space, without having to maintain separate base addresses for each initiator firewall and target firewall. As a result, application programs, for example, can execute transactions with increased performance on a computer system as compared to prior approaches.

公开(公告)号：US11573856B1

公开(公告)日：2023-02-07

申请号：US17477360

申请日：2021-09-16

Applicant: NVIDIA Corporation

Inventor： Michael Ditty ,  Hari U. Krishnan ,  Padam Patt Krishnani ,  Jyotirmaya Swain ,  Anirban Ghosh ,  Shraddha Manohar Gondkar ,  Avinash J V ,  Phanikumar Parvatham

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  G06F9/4401

Abstract: In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.

公开(公告)号：US20230036130A1

公开(公告)日：2023-02-02

申请号：US17477360

申请日：2021-09-16

Applicant: NVIDIA Corporation

Inventor： Michael Ditty ,  Hari U. Krishnan ,  Padam Patt Krishnani ,  Jyotirmaya Swain ,  Anirban Ghosh ,  Shraddha Manohar Gondkar ,  Avinash J V ,  Phanikumar Parvatham

IPC: G06F11/10 ,  G06F9/4401 ,  H03M13/09 ,  H03M13/00

Abstract: In various examples, a system includes a memory operating within a first risk level and circuitry operating within a second risk level that indicates more risk than the first risk level. The circuitry reads and/or writes data to a first memory address within the memory, and reads and/or writes an error detection code to a second memory address within the memory.