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公开(公告)号：US20140136891A1
公开(公告)日：2014-05-15
申请号：US13677085
申请日：2012-11-14
Applicant: NVIDIA CORPORATION
Inventor： Bruce Holmer , Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs , Magnus Ekman
IPC: G06F11/07
CPC classification number: G06F11/0793 , G06F9/3842 , G06F9/3865 , G06F11/004 , G06F11/0721 , G06F11/0763
Abstract: Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.
Abstract translation: 提供了与在管理头期间由微处理器生成/获得的潜在无效结果相关的实施例。 在一个示例中，用于操作微处理器的方法包括使微处理器在检测到跑道事件时进入跑道头。 示例性方法还包括在跑步头期间，确定与基于存储位置的指令相关联的操作将基于与存储位置相关联的架构毒性比特的值产生潜在的无效结果，并且响应于不同的操作。
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公开(公告)号：US20230100552A1
公开(公告)日：2023-03-30
申请号：US17929672
申请日：2022-09-02
Applicant: NVIDIA Corporation
Inventor： Albert Davies , Akash Bellubbi , Ashutosh Tadkase , Bruce Holmer , Suraj Das , Vishanth Iyer , Sever Topan , Ian Tramble , Linda Xiong , Sharat Janapareddy , Ranvijay Singh , John Lore
Abstract: One or more embodiments of the present disclosure relate to identifying, based on application data associated with a computing application that includes a set of runnables, a plurality of scheduling branches associated with scheduling execution of at least a subset of runnables of the set of runnables. Further, one or more embodiments relate to selecting a scheduling branch from the plurality of scheduling branches based at least on a coupling constraint that is applied to related runnables of at least the subset of runnables. The related runnables may include a first runnable that is designated for execution on a first compute engine and that triggers execution of a second runnable on a second compute engine. In addition, one or more embodiments may relate to determining an execution schedule of the set of runnables based at least on the scheduling branch.
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公开(公告)号：US20230096502A1
公开(公告)日：2023-03-30
申请号：US17929674
申请日：2022-09-02
Applicant: NVIDIA Corporation
Inventor： Ashutosh Tadkase , Akash Bellubbi , Ian Tramble , Peter Boonstoppel , Suraj Das , Ranvijay Singh , Sever Topan , Albert Davies , Linda Xiong , Sharat Janapareddy , Ashkan Vafaee , Sai Gurrappadi , Bruce Holmer , Vishanth Iyer , John Lore , Ian Howson , Pulkit Desai , Michael Cox
Abstract: One or more embodiments of the present disclosure relate to executing, by a plurality of compute engines, a plurality of runnables of a computing application based at least on an execution schedule and a set of commands associated with the execution schedule. The execution schedule may be generated using a compiling system to include the set of commands. The set of commands may include one or more individual commands corresponding to one or more timing fences dictating a timing and order of execution of one or more individual runnables of the plurality of runnables.
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公开(公告)号：US09740553B2
公开(公告)日：2017-08-22
申请号：US13677085
申请日：2012-11-14
Applicant: NVIDIA Corporation
Inventor： Bruce Holmer , Guillermo J. Rozas , Alexander Klaiber , James van Zoeren , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell D. Boggs , Magnus Ekman
CPC classification number: G06F11/0793 , G06F9/3842 , G06F9/3865 , G06F11/004 , G06F11/0721 , G06F11/0763
Abstract: Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.
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