公开(公告)号：US20240378089A1

公开(公告)日：2024-11-14

申请号：US18195305

申请日：2023-05-09

Applicant: NVIDIA Corporation

Inventor： David Allan Berson

IPC: G06F9/50 ,  G06F9/30

Abstract: Apparatuses, systems, and techniques to allocate and/or assign registers. In at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.

公开(公告)号：US20240169022A1

公开(公告)日：2024-05-23

申请号：US18072053

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F17/16 ,  G06F9/30

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/3009

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until matrix multiply-accumulate (MMA) memory transactions are performed.

公开(公告)号：US20240378035A1

公开(公告)日：2024-11-14

申请号：US18195301

申请日：2023-05-09

Applicant: NVIDIA Corporation

Inventor： David Allan Berson

IPC: G06F8/41

Abstract: Apparatuses, systems, and techniques to allocate and/or assign registers. In at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.

公开(公告)号：US20240169023A1

公开(公告)日：2024-05-23

申请号：US18072060

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to indicate whether matrix multiply-accumulate (MMA) memory operations are complete.

公开(公告)号：US20240378054A1

公开(公告)日：2024-11-14

申请号：US18195303

申请日：2023-05-09

Applicant: NVIDIA Corporation

Inventor： David Allan Berson

IPC: G06F9/30 ,  G06F9/48 ,  G06F11/34

Abstract: Apparatuses, systems, and techniques to allocate and/or assign registers. In at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.

公开(公告)号：US20240378041A1

公开(公告)日：2024-11-14

申请号：US18195295

申请日：2023-05-09

Applicant: NVIDIA Corporation

Inventor： David Allan Berson

IPC: G06F8/65 ,  G06F8/71 ,  G06F11/34

Abstract: Apparatuses, systems, and techniques to allocate and/or assign registers. In at least one embodiment, registers are allocated based, at least in part, on a set of estimated performance metrics associated with transformations generated prior to a register allocation phase of compilation.

公开(公告)号：US12204897B2

公开(公告)日：2025-01-21

申请号：US18072081

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

公开(公告)号：US20240168763A1

公开(公告)日：2024-05-23

申请号：US18072300

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F9/30 ,  G06F17/16

CPC classification number: G06F9/3001 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause two or more other computational operations to be performed by two or more streaming multiprocessors (SMs).

公开(公告)号：US20240168762A1

公开(公告)日：2024-05-23

申请号：US18072081

申请日：2022-11-30

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Kyrylo Perelygin ,  Maciej Tyrlik ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Balaji Krishna Yugandhar Atukuri ,  Rishkul Kulkarni ,  Konstantinos Kyriakopoulos ,  Edward H. Gornish ,  David Allan Berson ,  Bageshri Sathe ,  James Player ,  Aman Arora ,  Alan Kaatz ,  Andrew Kerr ,  Haicheng Wu ,  Cris Cecka ,  Vijay Thakkar ,  Sean Treichler ,  Jack H. Choquette ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Cody Addison ,  Girish Bhaskarrao Bharambe

IPC: G06F9/30 ,  G06F17/16

CPC classification number: G06F9/3001 ,  G06F9/3009 ,  G06F17/16

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.