公开(公告)号：US20240176515A1

公开(公告)日：2024-05-30

申请号：US18081547

申请日：2022-12-14

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Olivier Giroux ,  Jack H. Choquette ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Rui Guo ,  Chao Li ,  Vishalkumar Ketankumar Mehta ,  David Dastous St. Hilaire ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Subhasmita Chakraborty ,  Vikram Dhar

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Apparatuses, systems, and techniques to provide memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information about one or more memory transactions to be provided to one or more users.

公开(公告)号：US20240168794A1

公开(公告)日：2024-05-23

申请号：US18081537

申请日：2022-12-14

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Olivier Giroux ,  Jack H. Choquette ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Rui Guo ,  Chao Li ,  Vishalkumar Ketankumar Mehta ,  David Dastous St. Hilaire ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Subhasmita Chakraborty ,  Vikram Dhar

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/467 ,  G06F9/30087 ,  G06F9/3877 ,  G06F9/4881

Abstract: Apparatuses, systems, and techniques to store memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.

公开(公告)号：US20240168765A1

公开(公告)日：2024-05-23

申请号：US18086478

申请日：2022-12-21

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Stephen Anthony Bernard Jones ,  Alexander Lev Minkin ,  Olivier Giroux ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Aditya Avinash Atluri ,  Apoorv Parle ,  Ronny Meir Krashinsky ,  Alan Kaatz ,  Andrew Robert Kerr ,  Jack H. Choquette

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30047

Abstract: Apparatuses, systems, and techniques to perform a tensor prefetch instruction to cause one or more tensors to be stored into one or more caches. In at least one embodiment, one or more circuits of a GPU are to perform a tensor prefetch instruction to cause one or more tensors to be stored into one or more GPU caches.

公开(公告)号：US20240036956A1

公开(公告)日：2024-02-01

申请号：US17955163

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48 ,  G06F9/30

CPC classification number: G06F9/544 ,  G06F9/4881 ,  G06F9/30072

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within a group of blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction.

公开(公告)号：US20240036953A1

公开(公告)日：2024-02-01

申请号：US17955085

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/544 ,  G06F9/4881

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a scheduling policy of one or more blocks of one or more threads.

公开(公告)号：US20240036918A1

公开(公告)日：2024-02-01

申请号：US17955123

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/48 ,  G06F9/54 ,  G06F8/41

CPC classification number: G06F9/4881 ,  G06F9/545 ,  G06F8/456

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel.

公开(公告)号：US20230111125A1

公开(公告)日：2023-04-13

申请号：US17497731

申请日：2021-10-08

Applicant: NVIDIA Corporation

Inventor： Piotr Ciolkosz ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Wesley Maxey

IPC: G06F9/54 ,  G06F9/50

Abstract: Apparatuses, systems, and techniques to perform parallel processing. In at least one embodiment, a parallel processing algorithm for performing an additive prefix scan is selected from a plurality of alternatives based on an arrangement of a group of threads provided to perform the scan.

公开(公告)号：US20210294638A1

公开(公告)日：2021-09-23

申请号：US16825831

申请日：2020-03-20

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/52

Abstract: Apparatuses, systems, and techniques to parallelize operations in one or more programs with data copies from global memory to shared memory in each of the one or more programs. In at least one embodiment, a program performs operations on shared data and then asynchronously copies shared data to shared memory, and continues performing additional operations in parallel while the shared data is copied to shared memory until an indicator provided by an application programming interface to facilitate parallel computing, such as CUDA, informs said program that shared data has been copied to shared memory.

公开(公告)号：US20250123966A1

公开(公告)日：2025-04-17

申请号：US18381545

申请日：2023-10-18

Applicant: NVIDIA Corporation

Inventor： Harold Carter Edwards ,  Daniel Joseph Lustig ,  Gonzalo Brito Gadeschi ,  Subhasmita Chakraborty ,  Gokul Ramaswamy Hirisave Chandra Shekhara

IPC: G06F12/0811 ,  G06F12/0804

Abstract: Apparatuses, systems, and techniques to prevent information from being read from a second cache location while information is being stored in a first cache location. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to prevent information from being read from a second cache location while information is being stored in a first cache location.

公开(公告)号：US20240289129A1

公开(公告)日：2024-08-29

申请号：US18433741

申请日：2024-02-06

Applicant: NVIDIA Corporation

Inventor： Piotr Tomasz Ciolkosz ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gonzalo Brito Gadeschi ,  Georgii Evtushenko ,  Jake Hemstad ,  Vishalkumar Ketankumar Mehta ,  Michal Dominiak ,  Olivier Giroux ,  Konstantinos Kyriakopoulos

IPC: G06F9/30

CPC classification number: G06F9/3009 ,  G06F9/30181

Abstract: Apparatuses, systems, and techniques to perform an application programming interface (API) to select a single thread from a group of threads to perform a set of instructions. In at least one embodiment, processors or computer systems are to perform an API to indicate instructions to be performed by a single thread and to select that thread from a group of threads to perform said instructions.