公开(公告)号：US20240028400A1

公开(公告)日：2024-01-25

申请号：US17872621

申请日：2022-07-25

Applicant: NVIDIA Corporation

Inventor： Gaspar Mora Porta ,  Blaise Fanning ,  Michael Allen Parker ,  Manikandan Chandrasekaran ,  Adarsha Rao S J ,  Raghuram L

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F9/467

Abstract: In various examples, a transaction type of a transaction from a processing resource of a plurality of processing resources sharing a bus may be determined and used to track bandwidth usage for the processing resource with respect to a time slot. Transactions that indicate usage of downstream bandwidth may be distinguished from transactions that do not indicate usage of downstream bandwidth. Bandwidth usage for a time slot may be tracked using one or more counters. The system may block or permit transactions from reaching the bus based at least on the counter exceeding a threshold value. The total allocation of bandwidth to the processing resources sharing a bus may be limited to a value that is less than a maximum capability of the bus to allow for headroom. Bandwidth coming from different lines and/or lanes and belonging to the same processing resource may be shared.