公开(公告)号：US20240028400A1

公开(公告)日：2024-01-25

申请号：US17872621

申请日：2022-07-25

Applicant: NVIDIA Corporation

Inventor： Gaspar Mora Porta ,  Blaise Fanning ,  Michael Allen Parker ,  Manikandan Chandrasekaran ,  Adarsha Rao S J ,  Raghuram L

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F9/467

Abstract: In various examples, a transaction type of a transaction from a processing resource of a plurality of processing resources sharing a bus may be determined and used to track bandwidth usage for the processing resource with respect to a time slot. Transactions that indicate usage of downstream bandwidth may be distinguished from transactions that do not indicate usage of downstream bandwidth. Bandwidth usage for a time slot may be tracked using one or more counters. The system may block or permit transactions from reaching the bus based at least on the counter exceeding a threshold value. The total allocation of bandwidth to the processing resources sharing a bus may be limited to a value that is less than a maximum capability of the bus to allow for headroom. Bandwidth coming from different lines and/or lanes and belonging to the same processing resource may be shared.

公开(公告)号：US12105960B2

公开(公告)日：2024-10-01

申请号：US17900808

申请日：2022-08-31

Applicant: NVIDIA CORPORATION

Inventor： Srinivas Santosh Kumar Madugula ,  Olivier Giroux ,  Wishwesh Anil Gandhi ,  Michael Allen Parker ,  Raghuram L ,  Ivan Tanasic ,  Manan Patel ,  Mark Hummel ,  Alexander L. Minkin

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

公开(公告)号：US09886409B2

公开(公告)日：2018-02-06

申请号：US14715394

申请日：2015-05-18

Applicant: NVIDIA Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F17/50 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.

公开(公告)号：US20170212857A1

公开(公告)日：2017-07-27

申请号：US14715394

申请日：2015-05-18

Applicant: NVIDIA Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: An integrated circuit device comprises pin resources, a memory controller circuit, a network interface controller circuit, and transmitter circuitry. The pin resources comprise pads coupled to off-chip pins of the integrated circuit device. The memory controller circuit comprises a first interface and the network interface controller circuit comprises a second interface. The transmitter circuitry is configurable to selectively couple either a first signal of the first interface or a second signal of the second interface to a first pad of the pin resources based on a pin distribution between the first interface and the second interface.

公开(公告)号：US09742869B2

公开(公告)日：2017-08-22

申请号：US14101255

申请日：2013-12-09

Applicant: NVIDIA CORPORATION

Inventor： Evgeny Bolotin ,  Zvi Guz ,  Adwait Jog ,  Stephen William Keckler ,  Michael Allen Parker

IPC: H04L29/08

CPC classification number: H04L67/327

Abstract: A request management subsystem is configured to establish service classes for clients that issue requests for a shared resource on a computer system. The subsystem also is configured to determine the state of the system with respect to bandwidth, current latency, frequency and voltage levels, among other characteristics. Further, the subsystem is configured to evaluate the requirements of each client with respect to latency sensitivity and required bandwidth, among other characteristics. Finally, the subsystem is configured to schedule access to shared resources, based on the priority class of each client, the demands of the application, and the state of the system. With this approach, the subsystem may enable all clients to perform optimally or, alternatively, may cause all clients to experience an equal reduction in performance.

公开(公告)号：US09058453B2

公开(公告)日：2015-06-16

申请号：US13902701

申请日：2013-05-24

Applicant: NVIDIA Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F17/50

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.

Abstract translation: 提供了一种用于配置多个引脚资源的系统和方法。 该方法包括识别主要专用集成电路（ASIC）设备的多个引脚资源，并且基于第一接口和第二接口之间的引脚分配来配置多个引脚资源，其中第一接口提供第一通信路径 在主ASIC设备和第一设备之间，并且第二接口提供主ASIC设备和第二设备之间的第二通信路径。

公开(公告)号：US20140351780A1

公开(公告)日：2014-11-27

申请号：US13902701

申请日：2013-05-24

Applicant: Nvidia Corporation

Inventor： Stephen William Keckler ,  William J. Dally ,  Steven Lee Scott ,  Brucek Kurdo Khailany ,  Michael Allen Parker

IPC: G06F17/50

CPC classification number: G06F13/409 ,  G06F13/1668 ,  G06F13/4068 ,  G06F17/5054

Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.

Abstract translation: 提供了一种用于配置多个引脚资源的系统和方法。 该方法包括识别主要专用集成电路（ASIC）设备的多个引脚资源，并且基于第一接口和第二接口之间的引脚分配来配置多个引脚资源，其中第一接口提供第一通信路径 在主ASIC设备和第一设备之间，并且第二接口提供主ASIC设备和第二设备之间的第二通信路径。