公开(公告)号：US09766649B2

公开(公告)日：2017-09-19

申请号：US13947999

申请日：2013-07-22

Applicant: NVIDIA Corporation

Inventor： Stephen Felix ,  Jeffery Bond ,  Tezaswi Raja ,  Kalyana Bollapalli ,  Vikram Mehta

IPC: H03L1/00 ,  G06F1/08 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  H03L1/00 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.