公开(公告)号：US20230412131A1

公开(公告)日：2023-12-21

申请号：US17812292

申请日：2022-07-13

Applicant: NXP B.V.

Inventor： Achal Venkatesh ,  Gilles Montoriol ,  Birama Goumballa

IPC: H03F3/24 ,  G01S7/02

CPC classification number: H03F3/245 ,  H03F2200/451 ,  G01S7/02

Abstract: A power amplifier stage including multiple amplifier branch circuits, in which each amplifier branch circuit includes a cascode device, a source device, and a replica cascode device. The cascode device has current terminals coupled between an output node and an intermediate node, and has a control terminal receiving a corresponding activation signal. The source device has current terminals coupled between a supply reference node and the intermediate node, and has a control terminal receiving an input signal. The replica cascode device has current terminals coupled between a supply node and the intermediate node, and has a control terminal receiving a corresponding complementary activation signals. An output power level of the power amplifier stage is controlled by asserting a selected number of activation signals and corresponding complementary activation signals for activating a selected number of the amplifier branch circuits.

公开(公告)号：US20250119118A1

公开(公告)日：2025-04-10

申请号：US18484708

申请日：2023-10-11

Applicant: NXP B.V.

Inventor： Rajesh Prabhakar Shamala ,  Stephane Damien Thuriés ,  Achal Venkatesh ,  Erik Olieman

IPC: H03H11/04

Abstract: A device includes a filter circuit having both a transformer and a notch filter. The notch filter is formed via capacitive cross-coupling of windings of the transformer. The transformer includes a first winding with an input terminal and an output terminal and a second winding with an input terminal and an output terminal. The notch filter is formed by coupling a first capacitor between the input terminal of the first winding and the output terminal of the second winding, and by coupling a second capacitor between the output terminal of the first winding and the input terminal of the second winding.

公开(公告)号：US20240204870A1

公开(公告)日：2024-06-20

申请号：US18167136

申请日：2023-02-10

Applicant: NXP B.V.

Inventor： Achal Venkatesh ,  Birama Goumballa

IPC: H04B10/079 ,  H03F3/20 ,  H03M1/66

CPC classification number: H04B10/07955 ,  H03F3/20 ,  H03M1/66

Abstract: An integrated circuit includes a functional circuit and a power calibration and monitoring system including a digital-to-analog converter (DAC), a variable gain amplifier (VGA), and a counter. The DAC generates a differential pair of feedback currents based on a digital count. The VGA generates a differential pair of amplified signals based on a magnitude difference between the differential pair of feedback currents and a differential pair of detection currents derived from a differential pair of node voltages associated with the functional circuit. The counter generates the digital count based on the differential pair of amplified signals. The differential pair of feedback currents is controlled such that the magnitude difference between the differential pair of detection currents and the differential pair of feedback currents is within a tolerance limit. A power associated with the functional circuit is calibrated and monitored based on the digital count.