公开(公告)号：US20240062791A1

公开(公告)日：2024-02-22

申请号：US17821260

申请日：2022-08-22

Applicant: NXP B.V.

Inventor： Hubert Martin Bode ,  Alexander Hoefler ,  Glenn Charles Abeln

IPC: G11C7/10 ,  G11C7/14 ,  G11C5/14 ,  H03K19/094

CPC classification number: G11C7/1087 ,  G11C7/14 ,  G11C5/14 ,  H03K19/09421

Abstract: A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.