公开(公告)号：US20250052798A1

公开(公告)日：2025-02-13

申请号：US18788375

申请日：2024-07-30

Applicant: NXP B.V.

Inventor： Shilpa Gupta ,  Hubert Martin Bode ,  Rishi Bhooshan

IPC: G01R29/08 ,  H01L23/00 ,  H01L23/552

Abstract: A semiconductor device includes a secured circuit, an electromagnetic interference (EMI) sensor over a surface of the secured circuit, and a sensing circuit. The EMI sensor is configured to receive a reference voltage and the EMI sensor includes at least one of electric (E) field sensor or a magnetic (H) field sensor. The sensing circuit includes a hysteresis comparator and a voltage level comparator. The hysteresis comparator has a first input coupled to a first node of the EMI sensor via a low pass filter, a second input directly connected to the first node, and an output configured to provide an output indicative an EMI attack. An antenna portion of the EMI sensor includes the first node and is coupled between inputs of the voltage level comparator, in which the voltage comparator is configured to provide an output indicative of a physical tampering with the antenna portion.

公开(公告)号：US20240062791A1

公开(公告)日：2024-02-22

申请号：US17821260

申请日：2022-08-22

Applicant: NXP B.V.

Inventor： Hubert Martin Bode ,  Alexander Hoefler ,  Glenn Charles Abeln

IPC: G11C7/10 ,  G11C7/14 ,  G11C5/14 ,  H03K19/094

CPC classification number: G11C7/1087 ,  G11C7/14 ,  G11C5/14 ,  H03K19/09421

Abstract: A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.

公开(公告)号：US20240402845A1

公开(公告)日：2024-12-05

申请号：US18675524

申请日：2024-05-28

Applicant: NXP B.V.

Inventor： Sebastian Raschbacher ,  Hubert Martin Bode

IPC: G06F3/041 ,  G06F3/044

Abstract: A touch screen assembly and method of testing a capacitive touch screen are disclosed, during operation thereof in which a respectively unique drive signal is applied to each of a first plurality of lines, and each of a second plurality of lines is responsive thereto, wherein a change in a response on a one of the second plurality of lines to a one of the unique drives signals is indicative of a touch event at a cross-point of the respective ones, the method comprising: modifying an amplitude of the respective unique drive signal applied to each of the first plurality of lines; and in the event of identifying a response to each modified amplitude, on each of the second plurality of read lines, determining that the touch screen does not have a fault, and otherwise determining that the touch screen has a fault.