公开(公告)号：US20240062791A1

公开(公告)日：2024-02-22

申请号：US17821260

申请日：2022-08-22

Applicant: NXP B.V.

Inventor： Hubert Martin Bode ,  Alexander Hoefler ,  Glenn Charles Abeln

IPC: G11C7/10 ,  G11C7/14 ,  G11C5/14 ,  H03K19/094

CPC classification number: G11C7/1087 ,  G11C7/14 ,  G11C5/14 ,  H03K19/09421

Abstract: A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.

公开(公告)号：US20240203480A1

公开(公告)日：2024-06-20

申请号：US18535443

申请日：2023-12-11

Applicant: NXP B.V.

Inventor： Prokash Ghosh ,  Jyotirmoy Ghosh ,  Glenn Charles Abeln ,  Dwarka Prasad ,  Rajat Kohli ,  Jainendra Singh ,  Jwalant Kumar Mishra

IPC: G11C11/4078 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4078 ,  G11C11/4074 ,  G11C11/4076

Abstract: A memory power control unit, MPCU, is provided for preventing unauthorised access to data stored in a volatile memory, the MPCU comprising a power controller comprising an input configured to receive a signal from a tamper detection circuit, a first supply input configured 5 to receive a first supply voltage, a first reference input configured to receive a first reference voltage, a supply output configured to output a supply voltage to the volatile memory, a reference output configured to output a reference voltage to the volatile memory, wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output a reduced supply voltage via the supply 10 output for a first predetermined time period, wherein the reduced supply voltage is less than the first supply voltage.