公开(公告)号：US20220200718A1

公开(公告)日：2022-06-23

申请号：US17643096

申请日：2021-12-07

Applicant: NXP B.V.

Inventor： Martin Klein ,  Martin Kessel ,  Sebastian Bohn ,  Manfred Zupke ,  Evert-Jan Pol ,  Hendrik van der Ploeg ,  Andreas Johannes Gerrits ,  Prince Thomas

IPC: H04J3/06

Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.

公开(公告)号：US11757610B1

公开(公告)日：2023-09-12

申请号：US17659651

申请日：2022-04-18

Applicant: NXP B.V.

Inventor： Martin Kessel ,  Andreas Johannes Gerrits ,  Sebastian Bohn ,  Prince Thomas

IPC: H04L7/00 ,  H03L7/085

CPC classification number: H04L7/0008 ,  H03L7/085

Abstract: A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.

公开(公告)号：US11616590B2

公开(公告)日：2023-03-28

申请号：US17643096

申请日：2021-12-07

Applicant: NXP B.V.

Inventor： Martin Klein ,  Martin Kessel ,  Sebastian Bohn ,  Manfred Zupke ,  Evert-Jan Pol ,  Hendrik van der Ploeg ,  Andreas Johannes Gerrits ,  Prince Thomas

IPC: H04J3/06 ,  H04W56/00

Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.