公开(公告)号：US20250080127A1

公开(公告)日：2025-03-06

申请号：US18459219

申请日：2023-08-31

Applicant: NXP B.V.

Inventor： Michael Todd Berens ,  Khoi Mai ,  Ashutosh Jain ,  Dylan John Rosser

IPC: H03M1/08

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to an output of the DAC, a successive approximation register (SAR) logic unit coupled to an output of the comparator, and a programmable delay unit. The comparator includes a preamplifier having an input coupled to the output of the DAC and a latch having an input coupled to the output of the preamplifier and an output coupled to the input of the SAR logic unit. SAR logic unit generates a control signal, and programmable delay unit adjusts a delay between the control signal and a delayed control signal based on at least one parameter, such that comparator receives control signal and delayed control signal. In some implementations, the parameter is at least one of a frequency of a signal input to the DAC, a source impedance of a circuit driving the input signal, and a preamplifier power mode.