公开(公告)号：US20250080127A1

公开(公告)日：2025-03-06

申请号：US18459219

申请日：2023-08-31

Applicant: NXP B.V.

Inventor： Michael Todd Berens ,  Khoi Mai ,  Ashutosh Jain ,  Dylan John Rosser

IPC: H03M1/08

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to an output of the DAC, a successive approximation register (SAR) logic unit coupled to an output of the comparator, and a programmable delay unit. The comparator includes a preamplifier having an input coupled to the output of the DAC and a latch having an input coupled to the output of the preamplifier and an output coupled to the input of the SAR logic unit. SAR logic unit generates a control signal, and programmable delay unit adjusts a delay between the control signal and a delayed control signal based on at least one parameter, such that comparator receives control signal and delayed control signal. In some implementations, the parameter is at least one of a frequency of a signal input to the DAC, a source impedance of a circuit driving the input signal, and a preamplifier power mode.

公开(公告)号：US11984904B2

公开(公告)日：2024-05-14

申请号：US17662009

申请日：2022-05-04

Applicant: NXP B.V.

Inventor： Michael Todd Berens

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.

公开(公告)号：US20230361780A1

公开(公告)日：2023-11-09

申请号：US17662009

申请日：2022-05-04

Applicant: NXP B.V.

Inventor： Michael Todd Berens

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.

公开(公告)号：US20250141457A1

公开(公告)日：2025-05-01

申请号：US18384823

申请日：2023-10-27

Applicant: NXP B.V.

Inventor： Michael Todd Berens ,  Alphons Litjes ,  Erik Olieman

IPC: H03M1/06

Abstract: A SAR ADC includes a DAC, a comparator and SAR circuitry, where the DAC includes MSBs encoded with first capacitors; a mismatch error shaping capacitor coupled to the MSBs; LSBs encoded with second capacitors, where a first switch set couples bottom capacitor plates of the first capacitors and the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to first DAC feedback control signals, wherein a second switch set couples bottom capacitor plates of the second capacitors to receive the high reference voltage or the low reference voltage in response to second DAC feedback control signals, and wherein the SAR circuitry is configured to feedback a mismatch error value from a previous SAR conversion cycle to the LSBs sub-DAC during a current sampling cycle.

公开(公告)号：US11424754B1

公开(公告)日：2022-08-23

申请号：US17328740

申请日：2021-05-24

Applicant: NXP B.V.

Inventor： Michael Todd Berens

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/46

Abstract: Testing of the noise-shaping circuitry within a successive approximation register (“SAR”) analog-to-digital converter (“ADC”) (“SAR ADC”) to ensure it will function as expected, while also providing a method for calibrating the coefficients of the noise-shaping circuitry. Programmable/trimmable circuit component(s) can be used to calibrate the coefficient(s) of the SAR ADC. Digital logic within the SAR engine enables it to selectively skip portions of the ADC conversion process and to use voltage references rather than an analog voltage input signal in sample mode during such test/calibration modes.