公开(公告)号：US11683029B1

公开(公告)日：2023-06-20

申请号：US17648199

申请日：2022-01-18

Applicant: NXP B.V.

Inventor： Ashutosh Jain ,  Khoi Mai

IPC: H03K3/00 ,  H03K5/08 ,  H03K19/00 ,  G06F13/38 ,  G06F13/42 ,  H03K17/0812 ,  H03K17/10

CPC classification number: H03K17/08122 ,  H03K17/102

Abstract: A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

公开(公告)号：US11581875B1

公开(公告)日：2023-02-14

申请号：US17452276

申请日：2021-10-26

Applicant: NXP B.V.

Inventor： Khoi Mai ,  Ashutosh Jain

IPC: H03K19/00 ,  H03K3/011 ,  H04B1/04 ,  H03K19/0185 ,  H03K17/687 ,  H03K5/01

Abstract: In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

公开(公告)号：US20250080127A1

公开(公告)日：2025-03-06

申请号：US18459219

申请日：2023-08-31

Applicant: NXP B.V.

Inventor： Michael Todd Berens ,  Khoi Mai ,  Ashutosh Jain ,  Dylan John Rosser

IPC: H03M1/08

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to an output of the DAC, a successive approximation register (SAR) logic unit coupled to an output of the comparator, and a programmable delay unit. The comparator includes a preamplifier having an input coupled to the output of the DAC and a latch having an input coupled to the output of the preamplifier and an output coupled to the input of the SAR logic unit. SAR logic unit generates a control signal, and programmable delay unit adjusts a delay between the control signal and a delayed control signal based on at least one parameter, such that comparator receives control signal and delayed control signal. In some implementations, the parameter is at least one of a frequency of a signal input to the DAC, a source impedance of a circuit driving the input signal, and a preamplifier power mode.