公开(公告)号：US20250124976A1

公开(公告)日：2025-04-17

申请号：US18893493

申请日：2024-09-23

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Rajat Kohli ,  Ganesh Bhat ,  Jwalant Kumar Mishra

IPC: G11C11/418 ,  G11C5/06

Abstract: A memory includes at least one memory bank which includes a set of memory arrays. Each memory cell includes a plurality of memory cells. The at least one memory bank includes: multiple word lines each connected to a corresponding row of the memory cells; a first decoder configured to receive address data, and decode the address data to provide intermediate data; a second decoder located in a central area of the memory bank between ones of the set of memory arrays, and configured to receive the intermediate data from the first decoder, and decode the intermediate data to provide selection data to the word lines. Memory cells addressable by a respective word line designated by the selection data are configured to be addressable by means of that selection data.