公开(公告)号：US20140145297A1

公开(公告)日：2014-05-29

申请号：US13687842

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Roel DAAMEN ,  Gerhard KOOPS ,  Peter Gerard STEENEKEN

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a support, at least three metal layers above the support, the metal layers having a top metal layer with a top plate and a bottom metal layer with a bottom plate, dielectric material between the top and bottom plates to form a capacitor, and plural oxide layers above the support, such oxide layers including a top oxide layer, each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit by providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate.

Abstract translation: 集成电路包括支撑体，支撑体上方至少三个金属层，金属层具有顶部金属层，顶部金属层和具有底板的底部金属层，位于顶板和底板之间的介电材料，以形成电容器 ，以及支撑体上方的多个氧化物层，这些氧化物层包括顶部氧化物层，每个氧化物层分别覆盖相应的金属层。 顶部氧化物层覆盖顶部金属层，并具有露出顶板的至少一部分的开口。 通过提供包括底板的金属和氧化物层的支撑来形成集成电路的方法，形成露出底板的空腔，用电介质填充空腔，施加具有顶板和另外的氧化物层的另外的金属层 ，并形成开口以露出顶板。