公开(公告)号：US20130256825A1

公开(公告)日：2013-10-03

申请号：US13852978

申请日：2013-03-28

Applicant: NXP B.V.

Inventor： Aurelie HUMBERT ,  Roel DAAMEN ,  Viet Hoang NGUYEN

IPC: H01L27/16 ,  H01L37/00

CPC classification number: H01L27/16 ,  G01N27/18 ,  G01N33/004 ,  H01L37/00 ,  H01L37/02

Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a thermal conductivity based gas sensor having an electrically resistive sensor element located on the major surface for exposure to a gas to be sensed. The integrated circuit further includes a barrier located on the major surface for inhibiting a flow of the gas across the sensor element.

Abstract translation: 一种集成电路及其制造方法。 集成电路包括具有主表面的半导体衬底。 集成电路还包括基于导热系数的气体传感器，其具有位于主表面上的用于暴露于待感测气体的电阻传感器元件。 集成电路还包括位于主表面上的阻挡气体穿过传感器元件的阻挡层。

公开(公告)号：US20140342527A1

公开(公告)日：2014-11-20

申请号：US14449522

申请日：2014-08-01

Applicant: NXP B.V.

Inventor： Peter Gerard STEENEKEN ,  Roel DAAMEN ,  Gerard KOOPS ,  Jan SONSKY ,  Evelyne GRIDELET ,  Coenraad Cornelis TAK

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/823878

Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.

公开(公告)号：US20140145297A1

公开(公告)日：2014-05-29

申请号：US13687842

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Roel DAAMEN ,  Gerhard KOOPS ,  Peter Gerard STEENEKEN

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a support, at least three metal layers above the support, the metal layers having a top metal layer with a top plate and a bottom metal layer with a bottom plate, dielectric material between the top and bottom plates to form a capacitor, and plural oxide layers above the support, such oxide layers including a top oxide layer, each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit by providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate.

Abstract translation: 集成电路包括支撑体，支撑体上方至少三个金属层，金属层具有顶部金属层，顶部金属层和具有底板的底部金属层，位于顶板和底板之间的介电材料，以形成电容器 ，以及支撑体上方的多个氧化物层，这些氧化物层包括顶部氧化物层，每个氧化物层分别覆盖相应的金属层。 顶部氧化物层覆盖顶部金属层，并具有露出顶板的至少一部分的开口。 通过提供包括底板的金属和氧化物层的支撑来形成集成电路的方法，形成露出底板的空腔，用电介质填充空腔，施加具有顶板和另外的氧化物层的另外的金属层 ，并形成开口以露出顶板。