公开(公告)号：US20150098163A1

公开(公告)日：2015-04-09

申请号：US14045611

申请日：2013-10-03

Applicant: NXP B.V.

Inventor： Alessandro FERRARA ,  Luc van DIJK ,  Peter Gerard STEENEKEN

IPC: H02H5/04 ,  H03K5/08

CPC classification number: H02H5/044 ,  H02H5/04 ,  H03K5/08 ,  H03K17/0822 ,  H03K17/145 ,  H03K2017/0806

Abstract: A circuit for protecting a transistor is enclosed. The circuit includes a temperature sensing device coupled to the transistor and a tunable clamping circuit connected between transistor terminals, wherein the tunable clamping circuit is configured to provide an adjustable clamping voltage. A temperature controller coupled to the temperature sensing device and the tunable clamping circuit is also included. The temperature controller is configured to trigger a change in a clamping voltage of the tunable clamping circuit based on a feedback from the temperature sensing device.

Abstract translation: 封装保护晶体管的电路。 电路包括耦合到晶体管的温度感测装置和连接在晶体管端子之间的可调谐钳位电路，其中可调谐钳位电路被配置为提供可调整的钳位电压。 还包括耦合到温度感测装置和可调谐钳位电路的温度控制器。 温度控制器被配置为基于来自温度感测装置的反馈来触发可调谐钳位电路的钳位电压的变化。

公开(公告)号：US20140342527A1

公开(公告)日：2014-11-20

申请号：US14449522

申请日：2014-08-01

Applicant: NXP B.V.

Inventor： Peter Gerard STEENEKEN ,  Roel DAAMEN ,  Gerard KOOPS ,  Jan SONSKY ,  Evelyne GRIDELET ,  Coenraad Cornelis TAK

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/823878

Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.

公开(公告)号：US20140145297A1

公开(公告)日：2014-05-29

申请号：US13687842

申请日：2012-11-28

Applicant: NXP B.V.

Inventor： Roel DAAMEN ,  Gerhard KOOPS ,  Peter Gerard STEENEKEN

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a support, at least three metal layers above the support, the metal layers having a top metal layer with a top plate and a bottom metal layer with a bottom plate, dielectric material between the top and bottom plates to form a capacitor, and plural oxide layers above the support, such oxide layers including a top oxide layer, each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit by providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate.

Abstract translation: 集成电路包括支撑体，支撑体上方至少三个金属层，金属层具有顶部金属层，顶部金属层和具有底板的底部金属层，位于顶板和底板之间的介电材料，以形成电容器 ，以及支撑体上方的多个氧化物层，这些氧化物层包括顶部氧化物层，每个氧化物层分别覆盖相应的金属层。 顶部氧化物层覆盖顶部金属层，并具有露出顶板的至少一部分的开口。 通过提供包括底板的金属和氧化物层的支撑来形成集成电路的方法，形成露出底板的空腔，用电介质填充空腔，施加具有顶板和另外的氧化物层的另外的金属层 ，并形成开口以露出顶板。