Power management circuit
    2.
    发明授权

    公开(公告)号:US11368036B2

    公开(公告)日:2022-06-21

    申请号:US16860944

    申请日:2020-04-28

    Applicant: NXP B.V.

    Abstract: One example discloses a power management circuit, including: an ultrasonic transmitter configured to generate an ultrasonic signal having a set of transmitted ultrasonic signal attributes; an ultrasonic receiver configured to detect the ultrasonic signal having a set of received ultrasonic signal attributes; wherein the power management circuit is configured to cause a device to be operated at a first power level and a second power level; and a proximity detection circuit configured to transition the device from the first power level to the second power level in response to a preselected difference between the transmitted set of ultrasonic signal attributes and the received set of ultrasonic signal attributes.

    POWER MANAGEMENT CIRCUIT
    3.
    发明申请

    公开(公告)号:US20210336470A1

    公开(公告)日:2021-10-28

    申请号:US16860944

    申请日:2020-04-28

    Applicant: NXP B.V.

    Abstract: One example discloses a power management circuit, including: an ultrasonic transmitter configured to generate an ultrasonic signal having a set of transmitted ultrasonic signal attributes; an ultrasonic receiver configured to detect the ultrasonic signal having a set of received ultrasonic signal attributes; wherein the power management circuit is configured to cause a device to be operated at a first power level and a second power level; and a proximity detection circuit configured to transition the device from the first power level to the second power level in response to a preselected difference between the transmitted set of ultrasonic signal attributes and the received set of ultrasonic signal attributes.

    Multi-via redistribution layer for integrated circuits having solder balls

    公开(公告)号:US10192837B1

    公开(公告)日:2019-01-29

    申请号:US15849656

    申请日:2017-12-20

    Applicant: NXP B.V.

    Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.

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