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    SOLDERLESS INTER-COMPONENT JOINTS
    1.
    发明申请
    SOLDERLESS INTER-COMPONENT JOINTS 审中-公开

    公开(公告)号：US20190239361A1

    公开(公告)日：2019-08-01

    申请号：US15886820

    申请日：2018-02-01

    Applicant: NXP B.V.

    Inventor： Tsung Nan Lo ,  Chung Hsiung Ho

    IPC: H05K3/34 ,  H05K1/11 ,  H01L23/00 ,  H01L23/498

    CPC classification number: H05K3/3421 ,  B23K20/02 ,  B23K2101/36 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H05K1/111 ,  H05K2201/10636 ,  H05K2201/10689

    Abstract: In a die-substrate assembly, a copper inter-component joint is formed by bonding corresponding copper interconnect structures together directly, without using solder. The copper interconnect structures have distal layers of (111) crystalline copper that enable them to bond together at a relatively low temperature (e.g., below 300° C.) compared to the relatively high melting point (about 1085° C.) for the bulk copper of the rest of the interconnect structures. By avoiding the use of solder, the resulting inter-component joint will not suffer from the adverse IMC/EM effects of conventional, solder-based joints. The distal surfaces of the interconnect structures may be curved (e.g., one concave and the other convex) to facilitate mating the two structures and improve the reliability of the physical contact between the two interconnect structures. The bonding may be achieved using directed microwave radiation and microwave-sensitive flux, instead of uniform heating.

    DICING OF LOW-K WAFERS
    3.
    发明申请
    DICING OF LOW-K WAFERS 审中-公开
    低K波形的定位

    公开(公告)号：US20160148842A1

    公开(公告)日：2016-05-26

    申请号：US14552086

    申请日：2014-11-24

    Applicant: NXP B.V.

    Inventor： Chung Hsiung Ho ,  Bensonil Chan ,  Chien Kuo

    IPC: H01L21/78 ,  H01L21/66 ,  H01L23/544

    CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L22/34 ,  H01L2221/68327 ,  H01L2221/6834

    Abstract: Consistent with an example embodiment, there is a method for sawing a wafer substrate, the wafer substrate having a front-side surface containing active devices separated by saw lanes and a back-side surface having undergone back grinding, the saw lanes having process control monitor (PCM) devices present therein. The method comprises: with a blade of a first kerf, sawing the back-side surface in tracks corresponding to the saw lanes, to a first depth; laser grooving (LG) the saw lanes, to an LG depth, on the front-side surface of the wafer substrate until PCM devices are substantially removed, the LG having a preset beam diameter; and with a blade of a second kerf, the second kerf less than the first kerf, sawing the front-side surface of the wafer substrate about the center of the saw lanes until the active devices are separated from one another.

    Abstract translation: 与示例性实施例一致，存在锯切晶片衬底的方法，晶片衬底具有包含由锯条分隔开的有源器件的前侧表面和经过背面研磨的后侧表面，锯条具有过程控制监视器 （PCM）设备。 该方法包括：用第一切口的叶片将对应于锯条的轨道中的后侧表面锯切到第一深度; 激光切槽（LG）锯片，LG晶片基板前面的LG深度，直到PCM装置基本上被去除，LG具有预设的光束直径; 并且具有第二切口的刀片，所述第二切口小于所述第一切口，围绕所述锯条的中心锯绕所述晶片基板的前侧表面，直到所述有源装置彼此分离。

    Solderless inter-component joints
    4.
    发明授权
    Solderless inter-component joints 有权

    公开(公告)号：US10390440B1

    公开(公告)日：2019-08-20

    申请号：US15886820

    申请日：2018-02-01

    Applicant: NXP B.V.

    Inventor： Tsung Nan Lo ,  Chung Hsiung Ho

    IPC: B23K20/00 ,  H05K3/34 ,  H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  B23K20/02 ,  B23K101/36

    Abstract: In a die-substrate assembly, a copper inter-component joint is formed by bonding corresponding copper interconnect structures together directly, without using solder. The copper interconnect structures have distal layers of (111) crystalline copper that enable them to bond together at a relatively low temperature (e.g., below 300° C.) compared to the relatively high melting point (about 1085° C.) for the bulk copper of the rest of the interconnect structures. By avoiding the use of solder, the resulting inter-component joint will not suffer from the adverse IMC/EM effects of conventional, solder-based joints. The distal surfaces of the interconnect structures may be curved (e.g., one concave and the other convex) to facilitate mating the two structures and improve the reliability of the physical contact between the two interconnect structures. The bonding may be achieved using directed microwave radiation and microwave-sensitive flux, instead of uniform heating.

    Multi-via redistribution layer for integrated circuits having solder balls
    10.
    发明授权
    Multi-via redistribution layer for integrated circuits having solder balls 有权

    公开(公告)号：US10192837B1

    公开(公告)日：2019-01-29

    申请号：US15849656

    申请日：2017-12-20

    Applicant: NXP B.V.

    Inventor： Chung Hsiung Ho ,  Wayne Hsiao ,  Richard Te Gan ,  James Raymond Spehar

    IPC: H01L23/00

    Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.

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