公开(公告)号：US10192837B1

公开(公告)日：2019-01-29

申请号：US15849656

申请日：2017-12-20

Applicant: NXP B.V.

Inventor： Chung Hsiung Ho ,  Wayne Hsiao ,  Richard Te Gan ,  James Raymond Spehar

IPC: H01L23/00

Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.