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公开(公告)号:US11714772B2
公开(公告)日:2023-08-01
申请号:US17660393
申请日:2022-04-22
Applicant: NXP B.V.
CPC classification number: G06F13/4027 , G06F13/385 , G06F13/4204
Abstract: A communication device is configured to exchange regular data bidirectionally with counterpart communication device via a regular interface; and to exchange additional data bidirectionally with the counterpart device via an additional interface. The device has a regular pinout corresponding to the regular interface that enables communication of regular data with the counterpart device; and an additional pinout with at least one additional pin, corresponding to the additional interface that enables communication of additional data with the counterpart device. The device has default data handling circuitry communicatively coupled to the additional pin, and configured, in a default mode, to transmit and receive additional default data via the additional pin. The first device has additional function data handling circuitry communicatively coupled to the additional pin and configured, in an active mode, to transmit and receive additional function data via the additional interface.
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公开(公告)号:US20220342839A1
公开(公告)日:2022-10-27
申请号:US17660393
申请日:2022-04-22
Applicant: NXP B.V.
Abstract: A communication device is configured to exchange regular data bidirectionally with counterpart communication device via a regular interface; and to exchange additional data bidirectionally with the counterpart device via an additional interface. The device has a regular pinout corresponding to the regular interface that enables communication of regular data with the counterpart device; and an additional pinout with at least one additional pin, corresponding to the additional interface that enables communication of additional data with the counterpart device. The device has default data handling circuitry communicatively coupled to the additional pin, and configured, in a default mode, to transmit and receive additional default data via the additional pin. The first device has additional function data handling circuitry communicatively coupled to the additional pin and configured, in an active mode, to transmit and receive additional function data via the additional interface.
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