公开(公告)号：US09842776B2

公开(公告)日：2017-12-12

申请号：US14994590

申请日：2016-01-13

Applicant: NXP B.V.

Inventor： John Suman Nakka ,  Tonny Kamphuis ,  Roelf Anco Jacob Groenhuis

IPC: H01L21/78 ,  H01L21/02 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/304 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/11

Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.

公开(公告)号：US20170200646A1

公开(公告)日：2017-07-13

申请号：US14994590

申请日：2016-01-13

Applicant: NXP B.V.

Inventor： John Suman Nakka ,  Tonny Kamphuis ,  Roelf Anco Jacob Groenhuis

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/544 ,  H01L23/31 ,  H01L23/00 ,  H01L21/304 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/304 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/11

Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.