公开(公告)号：US11269633B1

公开(公告)日：2022-03-08

申请号：US17303746

申请日：2021-06-07

Applicant: NXP B.V.

Inventor： Kevin Bruce Traylor

IPC: G06F9/30 ,  G06F9/38

Abstract: A method is provided for executing instructions in a pipelined processor. The method includes receiving a plurality of instructions in the pipelined processor. A first instruction of the plurality of instructions has a first bit field for holding a value for indicating how many times execution of the first instruction is repeated. Also, the value is for indicating how many no operation (NOP) instructions follow a last iteration of the repeated first instruction. The number of repeated instructions plus the number of NOP instructions is equal to the number of pipeline stages in the pipelined processor. In another embodiment, a pipelined data processor is provided for executing the repeating instruction.

公开(公告)号：US11630668B1

公开(公告)日：2023-04-18

申请号：US17529804

申请日：2021-11-18

Applicant: NXP B.V.

Inventor： Kevin Bruce Traylor ,  Jayakrishnan Cheriyath Mundarath ,  Michael Andrew Fischer

IPC: G06F12/0875 ,  G06F9/30 ,  G06F7/575 ,  G06F9/38

Abstract: A processor including a pointer storage that stores pointer descriptors each including addressing information, an arithmetic logic unit (ALU) configured to execute an instruction which includes operand indexes each identifying a corresponding pointer descriptor, multiple address generation units (AGUs), each configured to translate addressing information from a corresponding pointer descriptors into memory addresses for accessing corresponding operands stored in a memory, and a smart cache. The smart cache includes a cache storage, and uses the memory addresses from the AGUs to retrieve and store operands from the memory into the cache storage, and to provide the stored operands to the ALU when executing the instruction. The smart cache replaces a register file used by a conventional processor for retrieving and storing operand information. The pointer operands include post-update capability that reduces instruction fetches. Wasted memory cycles associated with cache speculation are avoided.

公开(公告)号：US11775310B2

公开(公告)日：2023-10-03

申请号：US17455070

申请日：2021-11-16

Applicant: NXP B.V.

Inventor： Michael Andrew Fischer ,  Kevin Bruce Traylor

IPC: G06F13/14 ,  G06F9/38 ,  G06F9/30 ,  G06F13/28 ,  G06F7/575 ,  G06F7/544

CPC classification number: G06F9/3867 ,  G06F7/5443 ,  G06F7/575 ,  G06F9/3012 ,  G06F13/28

Abstract: A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.

公开(公告)号：US20230153114A1

公开(公告)日：2023-05-18

申请号：US17455070

申请日：2021-11-16

Applicant: NXP B.V.

Inventor： Michael Andrew Fischer ,  Kevin Bruce Traylor

IPC: G06F9/38 ,  G06F9/30 ,  G06F7/544 ,  G06F7/575 ,  G06F13/28

CPC classification number: G06F9/3867 ,  G06F9/3012 ,  G06F7/5443 ,  G06F7/575 ,  G06F13/28

Abstract: A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.