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公开(公告)号：US20230229445A1
公开(公告)日：2023-07-20
申请号：US17577577
申请日：2022-01-18
申请人： NXP B.V.
IPC分类号： G06F9/30
CPC分类号： G06F9/3013 , G06F9/30181
摘要： A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.
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公开(公告)号：US11755361B2
公开(公告)日：2023-09-12
申请号：US17502160
申请日：2021-10-15
申请人： NXP B.V.
CPC分类号： G06F9/4812 , G06F9/542 , H04J3/10
摘要： A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware devices.
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公开(公告)号：US11775310B2
公开(公告)日：2023-10-03
申请号：US17455070
申请日：2021-11-16
申请人： NXP B.V.
CPC分类号： G06F9/3867 , G06F7/5443 , G06F7/575 , G06F9/3012 , G06F13/28
摘要： A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.
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公开(公告)号：US20230153114A1
公开(公告)日：2023-05-18
申请号：US17455070
申请日：2021-11-16
申请人： NXP B.V.
CPC分类号： G06F9/3867 , G06F9/3012 , G06F7/5443 , G06F7/575 , G06F13/28
摘要： A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.
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公开(公告)号：US11153418B2
公开(公告)日：2021-10-19
申请号：US16669694
申请日：2019-10-31
申请人： NXP B.V.
IPC分类号： G06F15/173 , H04L29/06 , H04W4/40 , H04L1/00 , H04L5/00 , H04L29/08 , H04W28/06 , H04W52/26 , H04W52/34 , H04W84/12
摘要： Aspects of the disclosure are directed to methods and apparatuses for wireless vehicular communications involving the transmission of messages using two or more protocols. As may be implemented in accordance with one or more embodiments characterized herein, wireless station-to-station communications are carried out in which a plurality of stations share a wireless communications channel. Information is wirelessly collected respectively from transmissions associated with a legacy communication protocol and another type of communication protocol. A current communication environment of the station is dynamically discerned and characterizes a dynamic relationship of the collected information using the legacy communication protocol relative to the collected information using the other communication protocol. Communications are wirelessly transmitted over the wireless communications channel using the legacy and other communication protocols, by allocating usage of the channel through transmissions of data, via the legacy communication protocol and via the other communication protocol, based on the dynamic relationship.
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公开(公告)号：US11816486B2
公开(公告)日：2023-11-14
申请号：US17577577
申请日：2022-01-18
申请人： NXP B.V.
CPC分类号： G06F9/30123 , G06F9/3851 , G06F9/30127
摘要： A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.
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公开(公告)号：US20230266971A1
公开(公告)日：2023-08-24
申请号：US17586708
申请日：2022-01-27
申请人： NXP B.V.
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30112
摘要： Embodiments of a multithreaded processor and a method of assigning blocks of register files for hardware threads of multithreaded processors are disclosed. In an embodiment, the method includes providing a multithreaded processor with a register file that provides registers for T hardware threads, the register file being organized as a set of B blocks, where each of the B blocks contains N registers and where B is greater than or equal to T, configuring assignments of the B blocks to the T hardware threads such that at least one of the B blocks of the register file and not more than R/N of the B blocks of the register file is assigned to each of the T hardware threads, where R is the number of registers defined by the instruction set architecture of the multithreaded processor and where R/N is an integer, thereby the multithreaded processor supports the T hardware threads with the register file that has less than T×R registers, and executing machine instructions on the multithreaded processor, where register numbers in the machine instructions are translated into register file addresses using the configured assignments.
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公开(公告)号：US11726789B1
公开(公告)日：2023-08-15
申请号：US17586708
申请日：2022-01-27
申请人： NXP B.V.
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30112 , G06F9/30123
摘要： Embodiments of a multithreaded processor and a method of assigning blocks of register files for hardware threads of multithreaded processors are disclosed. In an embodiment, the method includes providing a multithreaded processor with a register file that provides registers for T hardware threads, the register file being organized as a set of B blocks, where each of the B blocks contains N registers and where B is greater than or equal to T, configuring assignments of the B blocks to the T hardware threads such that at least one of the B blocks of the register file and not more than R/N of the B blocks of the register file is assigned to each of the T hardware threads, where R is the number of registers defined by the instruction set architecture of the multithreaded processor and where R/N is an integer, thereby the multithreaded processor supports the T hardware threads with the register file that has less than T×R registers, and executing machine instructions on the multithreaded processor, where register numbers in the machine instructions are translated into register file addresses using the configured assignments.
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公开(公告)号：US20200162587A1
公开(公告)日：2020-05-21
申请号：US16669694
申请日：2019-10-31
申请人： NXP B.V.
IPC分类号： H04L29/06 , H04W28/06 , H04L5/00 , H04L1/00 , H04L29/08 , H04W4/40 , H04W84/12 , H04W52/26 , H04W52/34
摘要： Aspects of the disclosure are directed to methods and apparatuses for wireless vehicular communications involving the transmission of messages using two or more protocols. As may be implemented in accordance with one or more embodiments characterized herein, wireless station-to-station communications are carried out in which a plurality of stations (210, 212, 214) share a wireless communications channel. Information is wirelessly collected (213) respectively from transmissions associated with a legacy communication protocol and another type of communication protocol. A current communication environment of the station is dynamically discerned (211) and characterizes a dynamic relationship of the collected information using the legacy communication protocol relative to the collected information using the other communication protocol. Communications are wirelessly transmitted (216, 218, 219, 220) over the wireless communications channel using the legacy and other communication protocol, by allocating usage of the channel through transmissions of data, via the legacy communication protocol and via the other communication protocol, based on the dynamic relationship.
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公开(公告)号：US20230169163A1
公开(公告)日：2023-06-01
申请号：US17456738
申请日：2021-11-29
申请人： NXP B.V.
CPC分类号： G06F21/54 , G06F21/554 , G06F9/4812 , G06F9/3009 , G06F9/30101
摘要： An enhanced security of multiple software processes executing on a computer system is provided by isolating those processes from each other and from access to system hardware resources. Embodiments provide such isolation by executing kernel software that manages hardware and controls physical address space on a separate hardware thread (e.g., in an isolation domain) from the process threads executing application programs (e.g., in execution domains). This renders the software executing in the isolation domain safe from privilege escalation attacks and permits implementation of enforceable isolation between execution systems. A multithreaded processor having switch-on-event multithreading is used to provide software isolation and hardware-controlled handling of a subset of system services by a different hardware thread than the one requesting the service.
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