公开(公告)号：US09268351B2

公开(公告)日：2016-02-23

申请号：US14208180

申请日：2014-03-13

Applicant: NXP B.V.

Inventor： Philip Rutter ,  Maarten Swanenberg

IPC: G05F1/70 ,  H03K17/0814 ,  H03K17/567 ,  H01L27/06 ,  H01L27/088 ,  H03K17/687

CPC classification number: G05F1/70 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/0883 ,  H03K17/08148 ,  H03K17/567 ,  H03K2017/6875

Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.

Abstract translation: 一种半导体器件，包括以共源共栅配置布置的第一和第二场效应晶体管：其中所述第一场效应晶体管是耗尽型晶体管; 并且其中所述第二场效应晶体管包括第一源至栅极电容和第二附加源至栅极电容并联连接到所述第一源至栅极电容。 包括半导体器件的功率因数校正（PFC）电路。 包括PFC电路的电源。