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    SEMICONDUCTOR DEVICE AND A METHOD OF MAKING A SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND A METHOD OF MAKING A SEMICONDUCTOR DEVICE 审中-公开
    半导体器件和制造半导体器件的方法

    公开(公告)号：US20170077291A1

    公开(公告)日：2017-03-16

    申请号：US15233834

    申请日：2016-08-10

    Applicant: NXP B.V.

    Inventor： Steven Thomas Peake ,  Philip Rutter ,  Chris Rogers

    IPC: H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66

    CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/66734

    Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.

    Abstract translation: 半导体器件和制造半导体器件的方法。 该器件包括具有第一导电类型的半导体衬底，位于衬底上的掺杂硅层，延伸到硅层中的沟槽以及位于沟槽中的栅电极和栅极电介质。 器件还包括漏极区域，具有位于沟槽附近并位于漏极区域之上的具有第二导电类型的体区域，以及具有位于沟槽附近并位于身体区域上方的具有第一导电类型的源极区域。 位于身体区域下方的区域中的掺杂硅层包括通过补偿在所述区域内形成净掺杂浓度的施主离子和受体离子。 作为深度的函数的掺杂硅层的净掺杂浓度在位于身体区域正下方的区域中具有最小值。

    Vertical MOSFET transistor with a vertical capacitor region
    3.
    发明授权
    Vertical MOSFET transistor with a vertical capacitor region 有权
    具有垂直电容器区域的垂直MOSFET晶体管

    公开(公告)号：US09129991B2

    公开(公告)日：2015-09-08

    申请号：US14249204

    申请日：2014-04-09

    Applicant: NXP B.V.

    Inventor： Philip Rutter

    IPC: H01L27/108 ,  H01L29/94 ,  H01L29/66 ,  H01L29/78 ,  H01L27/07 ,  H01L25/07 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H01L29/66666 ,  H01L25/072 ,  H01L27/0733 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method to manufacture a vertical capacitor region that comprises a plurality of trenches, wherein the portions of the semiconductor region in between the trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.

    Abstract translation: 一种制造包括多个沟槽的垂直电容器区域的方法，其中沟槽之间的半导体区域的部分包括杂质。 这允许将沟槽放置得更靠近彼此，从而改善每单位面积比的电容。 器件的总电容由两个串联组件（即电介质衬垫两端的电容）和沟槽旁边的硅的耗尽电容来定义。 因此，电容器上的电压的增加会增加硅中的耗尽和耗尽电容，使得整体电容减小。 可以通过最小化可以通过确保与电容器相邻的硅尽可能高掺杂可以实现的耗尽区来抵消该效应。

    Cascode semiconductor device for power factor correction
    4.
    发明授权
    Cascode semiconductor device for power factor correction 有权
    用于功率因数校正的串联半导体器件

    公开(公告)号：US09268351B2

    公开(公告)日：2016-02-23

    申请号：US14208180

    申请日：2014-03-13

    Applicant: NXP B.V.

    Inventor： Philip Rutter ,  Maarten Swanenberg

    IPC: G05F1/70 ,  H03K17/0814 ,  H03K17/567 ,  H01L27/06 ,  H01L27/088 ,  H03K17/687

    CPC classification number: G05F1/70 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/0883 ,  H03K17/08148 ,  H03K17/567 ,  H03K2017/6875

    Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.

    Abstract translation: 一种半导体器件，包括以共源共栅配置布置的第一和第二场效应晶体管：其中所述第一场效应晶体管是耗尽型晶体管; 并且其中所述第二场效应晶体管包括第一源至栅极电容和第二附加源至栅极电容并联连接到所述第一源至栅极电容。 包括半导体器件的功率因数校正（PFC）电路。 包括PFC电路的电源。

    DIODE CIRCUIT AND POWER FACTOR CORRECTION BOOST CONVERTER USING THE SAME
    5.
    发明申请
    DIODE CIRCUIT AND POWER FACTOR CORRECTION BOOST CONVERTER USING THE SAME 有权
    二极管电路和功率因数校正升压转换器

    公开(公告)号：US20150229205A1

    公开(公告)日：2015-08-13

    申请号：US14613235

    申请日：2015-02-03

    Applicant: NXP B.V.

    Inventor： Henricus Cornelis Johannes Buthker ,  Matthias Rose ,  Philip Rutter ,  Jan Sonsky

    IPC: H02M1/42 ,  H02M7/06

    CPC classification number: H02M1/4225 ,  H02M3/155 ,  H02M7/06 ,  H02M2001/0048 ,  Y02B70/126 ,  Y02B70/1491 ,  Y02P80/112

    Abstract: Embodiments relate to a diode circuit which uses a Schottky diode. A parallel bypass branch has a switch and bypass diode in series. The operation of the switch is dependent on the voltage across the Schottky diode so that the bypass function is only effective when a desired voltage is reached. The diode circuit can be used as a replacement for a single diode, and provides bypass current protection preferably without requiring any external control input.

    Abstract translation: 实施例涉及使用肖特基二极管的二极管电路。 并联旁路支路具有串联的开关和旁路二极管。 开关的操作取决于肖特基二极管两端的电压，因此旁路功能仅在达到所需电压时有效。 二极管电路可以用作单个二极管的替代，并且提供旁路电流保护，优选地不需要任何外部控制输入。

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