公开(公告)号：US11074946B2

公开(公告)日：2021-07-27

申请号：US16705165

申请日：2019-12-05

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Jwalant Kumar Mishra ,  Patrick van de Steeg

IPC: G11C7/08 ,  G11C11/419 ,  G11C7/04 ,  G11C7/06 ,  G11C11/417

Abstract: A voltage differential sense amplifier circuit for a semiconductor memory circuit is disclosed. The voltage differential sense amplifier circuit includes a first and second pluralities of transistors. A first bias control circuit is included to bias the first plurality of transistors. The first bias control circuit is connected to body terminals of the first plurality of transistors for providing a temperature dependent first bias voltage to control threshold voltages of the first plurality of transistors. The temperature defendant first bias voltage is generated based on junction leakages at the body terminals of the first plurality of transistors. A second bias control circuit is included to bias the second plurality of transistors. The second bias control circuit is connected to body terminals of the second plurality of transistors for providing a temperature dependent second bias voltage to control threshold voltages of the second plurality of transistors. The temperature dependent second bias voltage is generated based on junction leakages at the body terminals of the second plurality of transistors.

公开(公告)号：US20210174845A1

公开(公告)日：2021-06-10

申请号：US16705165

申请日：2019-12-05

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Jwalant Kumar Mishra ,  Patrick van de Steeg

IPC: G11C7/08 ,  G11C11/419 ,  G11C11/417 ,  G11C7/06 ,  G11C7/04

Abstract: A voltage differential sense amplifier circuit for a semiconductor memory circuit is disclosed. The voltage differential sense amplifier circuit includes a first and second pluralities of transistors. A first bias control circuit is included to bias the first plurality of transistors. The first bias control circuit is connected to body terminals of the first plurality of transistors for providing a temperature dependent first bias voltage to control threshold voltages of the first plurality of transistors. The temperature defendant first bias voltage is generated based on junction leakages at the body terminals of the first plurality of transistors. A second bias control circuit is included to bias the second plurality of transistors. The second bias control circuit is connected to body terminals of the second plurality of transistors for providing a temperature dependent second bias voltage to control threshold voltages of the second plurality of transistors. The temperature dependent second bias voltage is generated based on junction leakages at the body terminals of the second plurality of transistors.

公开(公告)号：US09691496B1

公开(公告)日：2017-06-27

申请号：US15018194

申请日：2016-02-08

Applicant: NXP B.V.

Inventor： Rajat Kohli ,  Patrick van de Steeg ,  Jwalant Kumar Mishra ,  Pankaj Agarwal

IPC: G11C17/00 ,  G11C17/12

CPC classification number: G11C17/126 ,  G11C11/5692 ,  G11C17/12

Abstract: Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells.

公开(公告)号：US09406374B1

公开(公告)日：2016-08-02

申请号：US14882206

申请日：2015-10-13

Applicant: NXP B.V.

Inventor： Jainendra Singh ,  Pankaj Agarwal ,  Patrick van de Steeg ,  Jwalant Kumar Mishra

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: An apparatus includes a memory circuit and a word-line driver circuit. The memory circuit includes a plurality of rows of memory cells, each memory cell in a corresponding row having pass transistors connected to a shared word-line. The word-line driver circuit is configured and arranged to enable pass transistors of a first set of memory cells of the memory circuit by applying a first voltage to word-lines of the first set of memory cells, disable pass transistors of a second set of memory cells of the memory circuit by applying a second voltage to word-lines of the second set of memory cells, and mitigate leakage of pass transistors of a third set of memory cells of the memory circuit by applying a third voltage to word-lines of the third set of memory cells, wherein the third voltage is between the first and second voltages.

Abstract translation: 一种装置包括存储电路和字线驱动电路。 存储电路包括多行存储单元，相应行中的每个存储单元具有连接到共享字线的传输晶体管。 字线驱动器电路被配置和布置成通过对第一组存储器单元的字线施加第一电压来使能存储器电路的第一组存储单元的通过晶体管，禁用第二组存储器单元的字线 通过对第二组存储器单元的字线施加第二电压并且通过将第三电压施加到存储器电路的字线来减轻存储器电路的第三组存储器单元的传输晶体管的泄漏来减轻存储器电路的存储单元 第三组存储器单元，其中第三电压在第一和第二电压之间。