-
公开(公告)号：US11586238B1
公开(公告)日：2023-02-21
申请号：US17644356
申请日：2021-12-15
Applicant: NXP B.V.
Inventor： Robert Matthew Mertens , Ateet Omer , Sanjay Kumar Wadhwa , Charles Eric Seaberg
Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.
Search Results
1
records
(took 0.015 seconds)
筛选
AND
AND
过滤
NOT
NOT
Scan to Join
