公开(公告)号：US11876486B1

公开(公告)日：2024-01-16

申请号：US18154968

申请日：2023-01-16

Applicant: NXP B.V.

Inventor： Siyaram Sahu ,  Anand Kumar Sinha ,  Ateet Omer ,  Krishna Thakur

IPC: H03B5/36 ,  H03B5/06

CPC classification number: H03B5/06 ,  H03B5/362 ,  H03B5/366 ,  H03B2200/0062 ,  H03B2200/0082

Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.

公开(公告)号：US20250119098A1

公开(公告)日：2025-04-10

申请号：US18891556

申请日：2024-09-20

Applicant: NXP B.V.

Inventor： Harish Eleendram ,  Anand Kumar Sinha ,  Ateet Omer ,  Siyaram Sahu ,  Vishwajit Babasaheb Bugade

IPC: H03B5/36

Abstract: A compensation system for a crystal oscillator including a DC level comparator, current compensation circuitry, and a compensation controller. The crystal oscillator includes an amplifier with a feedback resistance coupled between first and second terminals of a crystal resonator. The DC level comparator may be a hysteretic comparator that compares a DC level of the first node with a DC level of the second node and to provide a corresponding compensation signal. The compensation controller controls a magnitude and direction of the compensation current applied to the first node by the current compensation circuitry based on the compensation signal. The current compensation circuitry sources current to or sinks current from the first node until the leakage current is minimized. The compensation controller may include a digital counter the generates a digital control value used to activate selected current sources or sinks for developing the compensation current.

公开(公告)号：US11586238B1

公开(公告)日：2023-02-21

申请号：US17644356

申请日：2021-12-15

Applicant: NXP B.V.

Inventor： Robert Matthew Mertens ,  Ateet Omer ,  Sanjay Kumar Wadhwa ,  Charles Eric Seaberg

IPC: G06F1/04 ,  H03K21/08 ,  H03M7/16 ,  H03K5/01 ,  H03K5/00

Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.