公开(公告)号：US09939496B2

公开(公告)日：2018-04-10

申请号：US14716595

申请日：2015-05-19

Applicant: NXP B.V.

Inventor： Edwin Schapendonk ,  Pieter Van Der Zee ,  Fabio Sebastiano ,  Robert Van Veldhoven

IPC: G01R33/02 ,  G01R33/00 ,  G01R33/09 ,  G01D5/16 ,  G01D5/14

CPC classification number: G01R33/0023 ,  G01D5/145 ,  G01D5/16 ,  G01D18/004 ,  G01R33/09

Abstract: A sensor system is disclosed. The sensor system includes a first sensor path comprising a first sensing element and a second sensing element being connected in series between a first supply terminal and a second supply terminal and an intermediate node connected in between the first supply terminal and the second supply terminal, a second sensor path comprising a third sensing element and a fourth sensing element connected in series between the first supply terminal and the second supply terminal, a first reference node connected in between the first supply terminal and the second supply terminal, and a second reference node connected in between the first supply terminal and the second supply terminal, and a processing unit to receive an input signal from the intermediate node, a first reference signal from the first reference node, and a second reference signal from the second reference node.

公开(公告)号：US10284220B1

公开(公告)日：2019-05-07

申请号：US16122637

申请日：2018-09-05

Applicant: NXP B.V.

Inventor： Robert Van Veldhoven ,  Alphons Litjes ,  Erik Olieman

IPC: G05F1/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/36 ,  H03M1/46

Abstract: The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.

公开(公告)号：US20190158108A1

公开(公告)日：2019-05-23

申请号：US16122637

申请日：2018-09-05

Applicant: NXP B.V.

Inventor： Robert Van Veldhoven ,  Alphons Litjes ,  Erik Olieman

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/06 ,  H03M1/36

Abstract: The present application relates to an EQ circuit, a method of operating it and a system comprising the EQ circuit and an ADC. The EQ circuit has a configurable load section, which is provided for selectively exposing one of a plurality of distinct loads to a reference source connected to a reference voltage signal input of the equalization circuit, and a logic section, which is arranged to accept a state signal from the ADC and to selectively connect one distinct load out of the plurality of distinct loads in response to the state signal. The state signal is indicative of an actual operation state of the ADC.