SYSTEM AND METHOD OF NOISE SCALING OF ANALOG TO DIGITAL CONVERSION SAMPLES BASED ON SUBSEQUENT FILTER COEFFICIENTS

    公开(公告)号:US20240267056A1

    公开(公告)日:2024-08-08

    申请号:US18106803

    申请日:2023-02-07

    Applicant: NXP B.V.

    CPC classification number: H03M1/124 H03M1/0626 H03M1/08

    Abstract: A system and method of analog to digital conversion including an adjustable ADC, FIR filter circuitry, and a noise setting controller. The ADC samples an analog input signal to provide digital samples at a sample rate that is Y times an output rate of output digital values. The FIR filter circuitry includes Y taps with Y corresponding coefficients and is configured to filter the digital samples from the ADC and to provide filtered digital samples at the sample rate. decimation circuitry may be included to decimate the filtered digital samples by Y to provide the output digital values. The noise setting controller provides an adjustment value to the ADC to adjust noise contribution of the digital samples provided by the ADC based on corresponding coefficients of the FIR filter circuitry. The ADC is adjusted to reduce noise contribution of digital samples that correspond with higher FIR filter coefficients.

    APPARATUS AND METHODS FOR OPTIMIZING COMBINED SENSING AND COMMUNICATIONS SYSTEMS

    公开(公告)号:US20230361464A1

    公开(公告)日:2023-11-09

    申请号:US18310848

    申请日:2023-05-02

    Applicant: NXP B.V.

    CPC classification number: H01Q3/2694 H01Q3/30

    Abstract: Systems and methods are provided for performing both wireless communications and wireless sensing in combination. The systems include at least a first base station having at least one antenna device where the antenna device includes a beamformer control unit that uses a modifiable lookup table to control beam characteristics. The system may send a first set of electromagnetic sensing beams to a first environmental area within a field of view of the at least one antenna device to detect environmental objects within the environmental area. Based on data received by the antenna device, the system may generate a modified lookup table.

    Capacitive sampling circuit
    5.
    发明授权

    公开(公告)号:US10958282B2

    公开(公告)日:2021-03-23

    申请号:US16813823

    申请日:2020-03-10

    Applicant: NXP B.V.

    Abstract: A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.

    CAPACITIVE SAMPLING CIRCUIT
    6.
    发明申请

    公开(公告)号:US20200313689A1

    公开(公告)日:2020-10-01

    申请号:US16813823

    申请日:2020-03-10

    Applicant: NXP B.V.

    Abstract: A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.

    SYSTEM AND METHOD OF EXTENDING INPUT RANGE OF ANALOG TO DIGITAL CONVERTER

    公开(公告)号:US20240405780A1

    公开(公告)日:2024-12-05

    申请号:US18205250

    申请日:2023-06-02

    Applicant: NXP B.V.

    Abstract: An analog to digital converter including a digital to analog converter (DAC), a comparator, and a controller. The DAC includes a sample node and a capacitor array controlled by a digital control input. The comparator compares a voltage of the sample node with a reference voltage to generate a comparison value. The controller presets the digital control input, prompts the DAC to sample the input voltage onto the sample node, resets the digital control input, and performs a conversion by successively adjusting the digital control input based on the comparison value to determine a digital output. A preset value is subtracted from the digital output to provide an adjusted digital output. A sample predictor predicts the next sample to determine the preset value used to adjust the sample node within a full scale range after DAC reset.

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