公开(公告)号：US11923840B1

公开(公告)日：2024-03-05

申请号：US18180167

申请日：2023-03-08

Applicant: NXP B.V.

Inventor： Chinmayee Kumari Panigrahi ,  Sunil Chandra Kasanyal ,  Shashank Sunil Amati

IPC: G06F1/24 ,  G06F1/28 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K17/6872 ,  G06F1/28 ,  H03K19/018571

Abstract: A power down signal generator generates a power down signal. The power down signal generator includes a detection transistor, a resistor coupled in series with the detection transistor, and a compensation transistor coupled in parallel to the resistor. The detection transistor receives a first supply voltage in a first voltage domain and a current. A control voltage is generated across the resistor based on a first part of the current. The compensation transistor receives a bias voltage derived from a second supply voltage in a second voltage domain and sinks, based on the bias voltage, a second part of the current to maintain the control voltage within a predefined range. The generation of the power down signal is controlled based on the first supply voltage and the control voltage.