公开(公告)号：US10079603B1

公开(公告)日：2018-09-18

申请号：US15947855

申请日：2018-04-08

Applicant: NXP B.V.

Inventor： Chinmayee Kumari Panigrahi

IPC: H03K19/0185 ,  H03K5/13 ,  H04L25/02

CPC classification number: H03K19/018528 ,  H03K5/13 ,  H03K19/018585 ,  H04L25/026 ,  H04L25/0272 ,  H04L25/0282

Abstract: A driver circuit for an integrated circuit (IC) is configurable to operate in three different signaling modes, namely, differential signaling mode, single-ended current mode, and single-ended voltage mode. The driver circuit receives first and second input signals from a pre-driver and outputs first and second output signals that conform with the selected one of the three signaling modes.

公开(公告)号：US20230139245A1

公开(公告)日：2023-05-04

申请号：US17452875

申请日：2021-10-29

Applicant: NXP B.V.

Inventor： Marcin Grad ,  Chinmayee Kumari Panigrahi ,  Maciej Skrobacki

IPC: H02H9/04 ,  H02H1/00

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

公开(公告)号：US12015407B1

公开(公告)日：2024-06-18

申请号：US18163347

申请日：2023-02-02

Applicant: NXP B.V.

Inventor： Chinmayee Kumari Panigrahi ,  Marcin Grad ,  Aman Chugh

IPC: H03K19/0175 ,  H03K3/356 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K3/35613 ,  H03K19/0008 ,  H03K19/00361 ,  H03K19/0175 ,  H03K19/018528

Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.

公开(公告)号：US20240195394A1

公开(公告)日：2024-06-13

申请号：US18163347

申请日：2023-02-02

Applicant: NXP B.V.

Inventor： Chinmayee Kumari Panigrahi ,  Marcin Grad ,  Aman Chugh

IPC: H03K3/356 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K3/35613 ,  H03K19/00361 ,  H03K19/018528

Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.

公开(公告)号：US11923840B1

公开(公告)日：2024-03-05

申请号：US18180167

申请日：2023-03-08

Applicant: NXP B.V.

Inventor： Chinmayee Kumari Panigrahi ,  Sunil Chandra Kasanyal ,  Shashank Sunil Amati

IPC: G06F1/24 ,  G06F1/28 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K17/6872 ,  G06F1/28 ,  H03K19/018571

Abstract: A power down signal generator generates a power down signal. The power down signal generator includes a detection transistor, a resistor coupled in series with the detection transistor, and a compensation transistor coupled in parallel to the resistor. The detection transistor receives a first supply voltage in a first voltage domain and a current. A control voltage is generated across the resistor based on a first part of the current. The compensation transistor receives a bias voltage derived from a second supply voltage in a second voltage domain and sinks, based on the bias voltage, a second part of the current to maintain the control voltage within a predefined range. The generation of the power down signal is controlled based on the first supply voltage and the control voltage.

公开(公告)号：US11855450B2

公开(公告)日：2023-12-26

申请号：US17452875

申请日：2021-10-29

Applicant: NXP B.V.

Inventor： Marcin Grad ,  Chinmayee Kumari Panigrahi ,  Maciej Skrobacki

IPC: H02H9/04 ,  H02H1/00

CPC classification number: H02H9/046 ,  H02H1/0007

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

公开(公告)号：US11804709B2

公开(公告)日：2023-10-31

申请号：US17452875

申请日：2021-10-29

Applicant: NXP B.V.

Inventor： Marcin Grad ,  Chinmayee Kumari Panigrahi ,  Maciej Skrobacki

IPC: H02H9/04 ,  H02H1/00

CPC classification number: H02H9/046 ,  H02H1/0007

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.