公开(公告)号：US20220375923A1

公开(公告)日：2022-11-24

申请号：US17374214

申请日：2021-07-13

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax ,  Dongyong Zhu ,  Feng Cong ,  Tingting Pan

IPC: H01L27/02

Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

公开(公告)号：US12205942B2

公开(公告)日：2025-01-21

申请号：US17374214

申请日：2021-07-13

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax ,  Dongyong Zhu ,  Feng Cong ,  Tingting Pan

IPC: H01L27/02

Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.