公开(公告)号：US11296499B2

公开(公告)日：2022-04-05

申请号：US16177323

申请日：2018-10-31

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Guido Wouter Willem Quax ,  Peter Christiaans

IPC: H02H9/04 ,  H01L27/02 ,  H01R13/648

Abstract: Embodiments of a method, a circuit and a system are disclosed. In an embodiment, a discharge protection circuit is disclosed. The discharge protection circuit includes a switch having a capacitive coupling between a gate and a drain of the switch, wherein the capacitive coupling facilitates a capacitively coupled current. The discharge protection circuit further includes a gate network including at least the gate of the switch, a gate control element and a resistor connected to the gate and the gate control element. In addition, the discharge protection circuit includes an electrostatic discharge rail that connects to a diode that is coupled to the gate and the resistor, wherein the capacitive coupling facilitates sinking of at least a part of an electrostatic discharge current via the gate network.

公开(公告)号：US09973000B2

公开(公告)日：2018-05-15

申请号：US15172208

申请日：2016-06-03

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Guido Wouter Willem Quax ,  Gijs Jan De Raad

IPC: H02H3/22 ,  H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0285

Abstract: An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.

公开(公告)号：US20220375923A1

公开(公告)日：2022-11-24

申请号：US17374214

申请日：2021-07-13

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax ,  Dongyong Zhu ,  Feng Cong ,  Tingting Pan

IPC: H01L27/02

Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

公开(公告)号：US20220085156A1

公开(公告)日：2022-03-17

申请号：US17473167

申请日：2021-09-13

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax ,  Dongyong Zhu

IPC: H01L29/06 ,  H01L27/02

Abstract: As disclosed herein, an integrated circuit substrate includes a first region coupled to a signal terminal and includes a guard region coupled via a diode circuit to a supply voltage terminal of the integrated circuit. The first region and the guard region are both of a first conductivity type. A cathode of the diode circuit is connected to the guard region and an anode of the diode circuit is connected to the supply voltage terminal. The first region and the guard region are separated by at least by a second region of the substrate that is of a second conductivity type opposite the first conductivity type.

公开(公告)号：US20240405013A1

公开(公告)日：2024-12-05

申请号：US18325503

申请日：2023-05-30

Applicant: NXP B.V.

Inventor： Gijs Jan de Raad ,  Guido Wouter Willem Quax

IPC: H01L27/02

Abstract: An electrostatic discharge circuit includes two or more GGNMOS transistors where each transistor includes two types of body contact regions. Body contact regions of one type are non substrate isolated from body contact regions of the other type. A body contact region of one type is electrically coupled to the source region of its transistor and a body contact region of the other type is electrically connected to at least one other body contact region of the same type of another GGNMOS transistor.

公开(公告)号：US12040357B2

公开(公告)日：2024-07-16

申请号：US17473167

申请日：2021-09-13

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax ,  Dongyong Zhu

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L29/0623 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0266 ,  H01L27/0296 ,  H01L27/0921

Abstract: As disclosed herein, an integrated circuit substrate includes a first region coupled to a signal terminal and includes a guard region coupled via a diode circuit to a supply voltage terminal of the integrated circuit. The first region and the guard region are both of a first conductivity type. A cathode of the diode circuit is connected to the guard region and an anode of the diode circuit is connected to the supply voltage terminal. The first region and the guard region are separated by at least by a second region of the substrate that is of a second conductivity type opposite the first conductivity type.

公开(公告)号：US09704850B2

公开(公告)日：2017-07-11

申请号：US15177858

申请日：2016-06-09

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax ,  Da-Wei Lai

IPC: H01L27/02 ,  H01L29/87 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/0262 ,  H01L23/5286 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/87

Abstract: An electrostatic discharge protection device including a silicon controlled rectifier. In one example, the silicon controlled rectifier includes a first n-type region located in a semiconductor substrate. The silicon controlled rectifier also includes a first p-type region located adjacent the first n-type region in the semiconductor substrate. The silicon controlled rectifier further includes an n-type contact region and a p-type contact region located in the first n-type region. The silicon controlled rectifier also includes an n-type contact region and a p-type contact region located in the first p-type region. The silicon controlled rectifier further includes a blocking region having a higher resistivity than the first p-type region. The blocking region is located between the n-type contact region and the p-type contact region in the first p-type region for reducing a trigger voltage of the silicon controlled rectifier.

公开(公告)号：US12205950B2

公开(公告)日：2025-01-21

申请号：US17657894

申请日：2022-04-04

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax

IPC: H01L27/02 ,  H01L27/07 ,  H01L27/092

Abstract: An integrated circuit includes a first semiconductor device with an N type region biased by a first terminal and a second semiconductor device with a second region. An N type guard region is located laterally between the N type region of the first semiconductor device and the second region. A P type region is isolated in the N type guard region and is biased by a second terminal. The N type guard region is either electrically coupled to the second terminal through a resistor circuit or is characterized as floating.

公开(公告)号：US20240170959A1

公开(公告)日：2024-05-23

申请号：US18056744

申请日：2022-11-18

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD circuit includes a first transistor, a second transistor, and a silicon-controlled rectifier (SCR) circuit. The first transistor includes a first current electrode coupled at a first node, and a second current electrode and a control electrode coupled at a first voltage supply node. The second transistor includes a first current electrode, a second current electrode, and a control electrode. The control electrode of the second transistor is coupled at a body electrode of the first transistor. The SCR circuit includes an anode electrode coupled at the first node, a cathode electrode coupled at the first voltage supply node, and a trigger input coupled at the first current electrode of the second transistor.

公开(公告)号：US09704851B2

公开(公告)日：2017-07-11

申请号：US15179162

申请日：2016-06-10

Applicant: NXP B.V.

Inventor： Gijs Jan De Raad ,  Guido Wouter Willem Quax

IPC: H01L29/74 ,  H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/0285 ,  H01L27/0292 ,  H01L29/7436

Abstract: A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or ESD protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate. A junction is formed at a boundary between the first region and the second region. Contact regions of the first conductivity type and the second conductivity type located in each of the first region and the second region. A further contact region of the second conductivity type is located in the second region, in between the contact region of the first conductivity type and the junction. The further contact region and the contact region of the second conductivity type in the second region are connected together for biasing the second region.