公开(公告)号：US20250125159A1

公开(公告)日：2025-04-17

申请号：US18484533

申请日：2023-10-11

Applicant: NXP B.V.

Inventor： Yu Ling Tsai ,  Yao Jung Chang ,  Yen-Chih Lin ,  Tzu Ya Fang ,  Jian Nian Chen ,  Yi-Hsuan Tsai

IPC: H01L21/60 ,  H01L21/56

Abstract: A semiconductor device having dismantlable structure is provided. The method includes forming a packaged semiconductor die by mounting the semiconductor die onto a package substrate in a flip chip orientation, attaching an interposer substrate over a backside of the semiconductor die, and encapsulating with an encapsulant the semiconductor die and remaining gap region between the package substrate and the interposer substrate. A bond pad of the semiconductor die is interconnected with a conductive trace of the package substrate. The interposer substrate includes a plurality of conductive pads exposed at a top surface and interconnected with the package substrate. A dismantlable structure is attached on the top surface of the interposer substrate. A first region of the dismantlable structure covers the plurality of conductive pads.

公开(公告)号：US20250157862A1

公开(公告)日：2025-05-15

申请号：US18509642

申请日：2023-11-15

Applicant: NXP B.V.

Inventor： Yu Ling Tsai ,  Yen-Chih Lin ,  Yi-Hsuan Tsai ,  Yao Jung Chang

IPC: H01L23/04 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/367 ,  H01L23/552

Abstract: A semiconductor device having an integrated lid structure is provided. The method includes mounting a semiconductor die within a cavity of a lid structure. An active side of the semiconductor die is substantially coplanar with a bottom surface of the lid structure. An encapsulant substantially fills a gap region between sidewalls of the semiconductor die and inner sidewall surfaces of the cavity.

公开(公告)号：US20250157986A1

公开(公告)日：2025-05-15

申请号：US18505364

申请日：2023-11-09

Applicant: NXP B.V.

Inventor： Yen-Chih Lin ,  Yi-Hsuan Tsai ,  Yu Ling Tsai ,  Yao Jung Chang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532

Abstract: A method of forming a die-in-die semiconductor device is provided. The method includes forming a first cavity in a backside of a first semiconductor die. The first semiconductor die has a back end of line (BEOL) region, a front end of line (FEOL) region, and a bulk region. A second semiconductor die is mounted in the first cavity. A bond pad of the second semiconductor die is interconnected through a bottom side of the first cavity with an embedded conductive trace of the BEOL region of the first semiconductor die.

公开(公告)号：US20250006598A1

公开(公告)日：2025-01-02

申请号：US18342809

申请日：2023-06-28

Applicant: NXP B.V.

Inventor： Yao Jung Chang ,  Tzu Ya Fang ,  Yu Ling Tsai ,  Jian Nian Chen ,  Yen-Chih Lin

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor device is provided. The method includes affixing a spacer structure to a bottom side of a plurality of leads of a leadframe. A semiconductor die is attached to a top side of a die pad of the leadframe. The semiconductor die, the leadframe, and the spacer structure are encapsulated with an encapsulant. Portions of the spacer structure and portions of the leads of the plurality of leads are exposed at a bottom side of the encapsulant.