公开(公告)号：US07906407B2

公开(公告)日：2011-03-15

申请号：US11926469

申请日：2007-10-29

申请人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

IPC分类号： H01L21/76

CPC分类号： H01L21/31116 ,  H01L21/76205 ,  H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.

摘要翻译： 具有负锥角的浅沟槽隔离结构及其形成方法。 根据等离子体蚀刻工艺蚀刻形成在半导体衬底上的氮化硅层，以形成其中具有负锥角的侧壁的第一开口。 蚀刻衬底以在第一开口下方形成沟槽。 二氧化硅填充开口和沟槽以形成浅沟槽隔离结构，其中开口中的二氧化硅呈现负锥角，以避免在随后的工艺步骤期间形成导电条。

公开(公告)号：US20090127651A1

公开(公告)日：2009-05-21

申请号：US12356600

申请日：2009-01-21

申请人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

发明人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76232

摘要： In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

摘要翻译： 在半导体衬底中，具有设置在沟槽填充材料的空隙中的介电材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法。 在电介质材料形成在沟槽中之后，可以在湿式清洁工艺期间形成空隙。 在衬底上和空隙中形成保形氮化硅层。 在移除氮化硅层之后，空隙至少部分地被氮化硅材料填充。

公开(公告)号：US08022481B2

公开(公告)日：2011-09-20

申请号：US12356600

申请日：2009-01-21

申请人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

发明人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/31116 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76232

摘要： In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

摘要翻译： 在半导体衬底中，具有设置在沟槽填充材料的空隙中的介电材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法。 在电介质材料形成在沟槽中之后，可以在湿式清洁工艺期间形成空隙。 在衬底上和空隙中形成保形氮化硅层。 在移除氮化硅层之后，空隙至少部分地被氮化硅材料填充。

公开(公告)号：US07514336B2

公开(公告)日：2009-04-07

申请号：US11321206

申请日：2005-12-29

申请人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

发明人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L21/76

CPC分类号： H01L21/31116 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76232

摘要： In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

摘要翻译： 在半导体衬底中，具有设置在沟槽填充材料的空隙中的介电材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法。 在电介质材料形成在沟槽中之后，可以在湿式清洁工艺期间形成空隙。 在衬底上和空隙中形成保形氮化硅层。 在移除氮化硅层之后，空隙至少部分地被氮化硅材料填充。

公开(公告)号：US07141486B1

公开(公告)日：2006-11-28

申请号：US11153893

申请日：2005-06-15

申请人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying the first trench. Silicon dioxide fills both the first and the second trenches to form the shallow trench isolation structure, with the silicon dioxide in the first trench exhibiting a negative taper angle to avoid formation of polysilicon stringers during a gate polysilicon deposition.

摘要翻译： 具有负锥角的浅沟槽隔离结构。 梯度掺杂牺牲层形成在半导体衬底之上，并被蚀刻以形成其中具有呈负锥度角的沟槽侧壁的第一沟槽。 衬底也被蚀刻以在其中覆盖第一沟槽上形成第二沟槽。 二氧化硅填充第一和第二沟槽两者以形成浅沟槽隔离结构，其中第一沟槽中的二氧化硅呈现负锥角，以避免在栅极多晶硅沉积期间形成多晶硅桁条。

公开(公告)号：US07776678B2

公开(公告)日：2010-08-17

申请号：US12208929

申请日：2008-09-11

申请人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

发明人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

IPC分类号： H01L21/8238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

摘要翻译： 一种用于形成根据该方法形成的BiCMOS集成电路和结构的方法。 在用于CMOS器件的掺杂阱和栅极堆叠以及用于双极结型晶体管的集电极和基极区域之后，在发射极窗口内形成发射极层。 在发射极层上形成介电材料层，并且在蚀刻发射极层和去除蚀刻掩模期间保持原位。 在源极/漏极注入掺杂和注入源极/漏极掺杂剂的激活期间，电介质材料层进一步保持就位。 介电材料层用作热障，以限制在激活步骤期间发射体掺杂物的扩散。

公开(公告)号：US07439119B2

公开(公告)日：2008-10-21

申请号：US11361430

申请日：2006-02-24

申请人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

发明人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

摘要翻译： 一种用于形成根据该方法形成的BiCMOS集成电路和结构的方法。 在用于CMOS器件的掺杂阱和栅极堆叠以及用于双极结型晶体管的集电极和基极区域之后，在发射极窗口内形成发射极层。 在发射极层上形成介电材料层，并且在蚀刻发射极层和去除蚀刻掩模期间保持原位。 在源极/漏极注入掺杂和注入源极/漏极掺杂剂的激活期间，电介质材料层进一步保持就位。 介电材料层用作热障，以限制在激活步骤期间发射体掺杂物的扩散。

公开(公告)号：US20090011553A1

公开(公告)日：2009-01-08

申请号：US12208929

申请日：2008-09-11

申请人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

发明人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

IPC分类号： H01L21/8238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

摘要翻译： 一种用于形成根据该方法形成的BiCMOS集成电路和结构的方法。 在用于CMOS器件的掺杂阱和栅极堆叠以及用于双极结型晶体管的集电极和基极区域之后，在发射极窗口内形成发射极层。 在发射极层上形成介电材料层，并且在蚀刻发射极层和去除蚀刻掩模期间保持原位。 在源极/漏极注入掺杂和注入源极/漏极掺杂剂的激活期间，电介质材料层进一步保持就位。 介电材料层用作热障，以限制在激活步骤期间发射体掺杂物的扩散。

公开(公告)号：US07247556B2

公开(公告)日：2007-07-24

申请号：US11068237

申请日：2005-02-28

申请人： Arun K. Nanda ,  Nace Rossi

发明人： Arun K. Nanda ,  Nace Rossi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

摘要翻译： 一种制造集成电路（IC）的方法，其中通过适当地控制IC多层互连结构的层堆叠的一个或多个服务层中的固有应力来控制晶片翘曲。 在一个实施例中，多层互连结构的每个互连级别具有电介质层，形成在电介质层上的导电层，以及形成在导电层上的功能抗反射涂层（ARC）层。 每个ARC层由氮氧化硅形成，使得对应于不同互连级别的至少两个ARC层具有不同的固有应力。 每个ARC层中的固有应力的量被控制，例如通过控制层沉积期间的温度和/或气体组成。

公开(公告)号：US08084313B2

公开(公告)日：2011-12-27

申请号：US12832110

申请日：2010-07-08

申请人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

发明人： Arun K. Nanda ,  Venkat Raghavan ,  Nace Rossi

IPC分类号： H01L21/8238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

摘要翻译： 一种用于形成根据该方法形成的BiCMOS集成电路和结构的方法。 在用于CMOS器件的掺杂阱和栅极堆叠以及用于双极结型晶体管的集电极和基极区域之后，在发射极窗口内形成发射极层。 在发射极层上形成介电材料层，并且在蚀刻发射极层和去除蚀刻掩模期间保持原位。 在源极/漏极注入掺杂和注入源极/漏极掺杂剂的激活期间，电介质材料层进一步保持就位。 介电材料层用作热障，以限制在激活步骤期间发射体掺杂物的扩散。