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公开(公告)号：US4085675A
公开(公告)日：1978-04-25
申请号：US748621
申请日：1976-11-29
CPC分类号： B41L19/00
摘要： An apparatus for imprinting the raised indicia from a credit card on a copy sheet has a support provided with a holder for the credit card. A printing head is movable on the support between a raised position spaced from the holder and a lowered position juxtaposed therewith. In this lowered position an electrical actuator in the head can roll a platen roller across the card to imprint indicia on the card on a copy sheet overlying the card. An electromagnet in the support holds the head in the lowered position during the printing cycle. Switches are provided to energize the actuator once the head is fully in the lowered position and to deenergize the holding electromagnet after the printing cycle is completed so that the head can return to the raised position.
摘要翻译： 用于将信号卡上的凸起标记印在复印纸上的装置具有用于信用卡的持有人的支持。 打印头可以在支撑件之间在与保持器间隔开的升高位置和与其并置的下降位置之间移动。 在该降低的位置，头部中的电致动器可以滚动横过卡的压印辊，以将卡片上的标记印在覆盖该卡的复印纸上。 支架中的电磁铁在打印周期中将头部保持在降低位置。 提供开关以在头部完全处于降低位置时致动致动器，并且在打印周期完成之后使保持电磁体断电，使得头部能够返回到升高位置。
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公开(公告)号：US06259694B1
公开(公告)日：2001-07-10
申请号：US09049877
申请日：1998-03-27
申请人： Sadaharu Sato , Takayasu Muto , Tetsuya Aoki
发明人： Sadaharu Sato , Takayasu Muto , Tetsuya Aoki
IPC分类号： H04J306
CPC分类号： H04L12/40058 , H04J3/0685 , H04L12/40071 , H04L12/40117 , H04L69/08 , H04L69/28
摘要： A signal processing circuit which enables an error bit to be set simply without causing an increase in the size of the circuit even if the packet size is changed and which enables realization of stable operation without the system stopping even if the value of the time stamp is impossible. A pre-reception processing circuit decides if a received packet is normally continuous or discontinuous from data in the DBC region of the CIP header. When deciding it is discontinuous, it sets an error bit ERM allocated to one bit of the upper significant 7 bits of the source packet header to “1”, and writes this in an FIFO. A post-reception processing circuit, when reading from the FIFO, outputs the data stored in the FIFO to the application side when the error bit ERM is “0” and resets the error bit and outputs a dummy error packet when the error bit EMR is “1”.
摘要翻译： 一种信号处理电路，即使分组大小发生变化也能够简单地设定错误位而不引起电路尺寸的增加，即使时间戳的值为 不可能。 预接收处理电路判定所接收的分组是否正常连续或不连续的来自CIP头部的DBC区域中的数据。 当判定为不连续时，它将分配给源包头的高有效7位的一位的错误位ERM设置为“1”，并将其写入FIFO。 当从FIFO读取时，接收后处理电路当错误位ERM为“0”时将存储在FIFO中的数据输出到应用端，并且当错误位EMR为“0”时，复位错误位并输出虚拟错误包 “1”。
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公开(公告)号：US20070028276A1
公开(公告)日：2007-02-01
申请号：US11543403
申请日：2006-10-04
CPC分类号： H04N21/4147 , H04H40/90 , H04H60/27 , H04H60/80 , H04N5/4401 , H04N7/162 , H04N21/4117 , H04N21/42646 , H04N21/4334 , H04N21/434 , H04N21/436 , H04N21/440218 , H04N21/8106
摘要： In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.
摘要翻译： 在数字广播接收装置中，通过数字广播方式提供的数字广播信号被提供给各种类型的外部单元，并被有效地利用。 在上述装置中，解扰器解扰从前端单元输出的传输流，并将其提供给数字接口和解复用器。 解复用器从传输流中提取由用户指定的节目的压缩视频信号和压缩音频信号，并将所提取的信号提供给MPEG解码器。 MPEG解码器解压缩所提供的视频信号和音频信号，并将其提供给数字接口，NTSC编码器和音频信号D / A转换器。 数字接口在控制器的控制下将传输流或解压缩数据中的任何一个提供给数字外部单元。
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公开(公告)号：US08032919B2
公开(公告)日：2011-10-04
申请号：US11543403
申请日：2006-10-04
IPC分类号： H04N7/16
CPC分类号： H04N21/4147 , H04H40/90 , H04H60/27 , H04H60/80 , H04N5/4401 , H04N7/162 , H04N21/4117 , H04N21/42646 , H04N21/4334 , H04N21/434 , H04N21/436 , H04N21/440218 , H04N21/8106
摘要： In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.
摘要翻译： 在数字广播接收装置中，通过数字广播方式提供的数字广播信号被提供给各种类型的外部单元，并被有效地利用。 在上述装置中，解扰器解扰从前端单元输出的传输流，并将其提供给数字接口和解复用器。 解复用器从传输流中提取由用户指定的节目的压缩视频信号和压缩音频信号，并将所提取的信号提供给MPEG解码器。 MPEG解码器解压缩所提供的视频信号和音频信号，并将其提供给数字接口，NTSC编码器和音频信号D / A转换器。 数字接口在控制器的控制下将传输流或解压缩数据中的任何一个提供给数字外部单元。
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公开(公告)号：US06408012B1
公开(公告)日：2002-06-18
申请号：US09132823
申请日：1998-08-12
申请人： Sadaharu Sato
发明人： Sadaharu Sato
IPC分类号： H04J322
CPC分类号： H04L12/40117 , H04J3/0632 , H04L12/6418 , H04L2012/6483
摘要： A signal processing circuit which can effectively use a serial interface bus, provided with transmission processing circuits and a link core for dividing or synthesizing an input transport stream packet based on a number of divided blocks or a number of synthesized packets set in advance in accordance with the input rate, adding a time stamp which suppresses jitter at the serial interface bus and determines the output time of the data at the reception side, and sends the same to the serial interface bus.
摘要翻译： 一种能够有效地使用串行接口总线的信号处理电路，其具有传输处理电路和链路核心，用于根据分割块的数量或预先设置的合成数据包的数量来分类或合成输入的传输流分组 输入速率，添加抑制串行接口总线抖动的时间戳，并确定接收端数据的输出时间，并将其发送到串行接口总线。
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公开(公告)号：US06965995B1
公开(公告)日：2005-11-15
申请号：US09442727
申请日：1999-11-18
申请人： Sadaharu Sato
发明人： Sadaharu Sato
IPC分类号： G06F13/38 , G06F21/10 , H04L9/00 , H04L9/12 , H04L9/18 , H04L12/28 , H04L12/70 , H04L29/06 , H04N7/16
CPC分类号： H04L12/6418 , H04L9/0637 , H04L63/0428 , H04L63/20
摘要： A signal processing circuit capable of preventing illicit copies, preventing the circuit from being unable to discriminate a plurality of cipher mode and unable to decipher, and correctly decipher received data at the reception side, configured to be provided with a cipher mode continuity discrimination circuit which confirms the continuity of a cipher mode at the time of reading transmission data from an FIFO when transmitting a plurality of packets, stops the transmission when a discontinuity is confirmed even if there is room in a band enabling transmission in the transmission cycle of the 1394 standard, and instructs a link core to transmit the packet enciphered by a different cipher key at the next cycle, so that only the data enciphered by one cipher mode is transmitted within one cycle of the 1394 standards, and the data enciphered by a different cipher mode is transmitted in the next cycle.
摘要翻译： 一种能够防止非法复制的信号处理电路，防止电路不能区分多个密码模式并且不能解密，并且正确地解码接收侧的接收数据，配置为提供密码模式连续性判别电路 确认在发送多个分组时从FIFO读取发送数据时的密码模式的连续性，即使在1394标准的传输周期中能够进行传输的频带中有空间，当确认不连续性时停止发送 并且指示链路核心在下一个周期发送由不同密码密钥加密的分组，使得只有在1394标准的一个周期内仅传输一个加密模式加密的数据，并且以不同密码模式加密的数据 在下一个周期中传输。
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公开(公告)号：US06467093B1
公开(公告)日：2002-10-15
申请号：US09244282
申请日：1999-02-03
IPC分类号： H04N716
CPC分类号： H04N21/4147 , H04H40/90 , H04H60/27 , H04H60/80 , H04N5/4401 , H04N7/162 , H04N21/4117 , H04N21/42646 , H04N21/4334 , H04N21/434 , H04N21/436 , H04N21/440218 , H04N21/8106
摘要： In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.
摘要翻译： 在数字广播接收装置中，通过数字广播方式提供的数字广播信号被提供给各种类型的外部单元，并被有效地利用。 在上述装置中，解扰器解扰从前端单元输出的传输流，并将其提供给数字接口和解复用器。 解复用器从传输流中提取由用户指定的节目的压缩视频信号和压缩音频信号，并将所提取的信号提供给MPEG解码器。 MPEG解码器解压缩所提供的视频信号和音频信号，并将其提供给数字接口，NTSC编码器和音频信号D / A转换器。 数字接口在控制器的控制下将传输流或解压缩数据中的任何一个提供给数字外部单元。
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公开(公告)号：US06463060B1
公开(公告)日：2002-10-08
申请号：US09872964
申请日：2001-06-01
申请人： Sadaharu Sato , Takayasu Muto , Tetsuya Aoki
发明人： Sadaharu Sato , Takayasu Muto , Tetsuya Aoki
IPC分类号： H04J306
CPC分类号： H04L12/40058 , H04J3/0685 , H04L12/40071 , H04L12/40117 , H04L69/08 , H04L69/28
摘要： A signal processing circuit which enables an error bit to be set simply without causing an increase in the size of the circuit even if the packet size is changed and which enables realization of stable operation without the system stopping even if the value of the time stamp is impossible. A pre-reception processing circuit decides if a received packet is normally continuous or discontinuous from data in the DBC region of the CIP header. When deciding it is discontinuous, it sets an error bit ERM allocated to one bit of the upper significant 7 bits of the source packet header to “1”, and writes this in an FIFO. A post-reception processing circuit, when reading from the FIFO, outputs the data stored in the FIFO to the application side when the error bit ERM is “0” and resets the error bit and outputs a dummy error packet when the error bit EMR is “1”.
摘要翻译： 一种信号处理电路，即使分组大小发生变化也能够简单地设定错误位而不引起电路尺寸的增加，即使时间戳的值为 不可能。 预接收处理电路判定所接收的分组是否正常连续或不连续的来自CIP头部的DBC区域中的数据。 当判定为不连续时，它将分配给源包头的高有效7位的一位的错误位ERM设置为“1”，并将其写入FIFO。 当从FIFO读取时，接收后处理电路当错误位ERM为“0”时将存储在FIFO中的数据输出到应用端，并且当错误位EMR为“0”时，复位错误位并输出虚拟错误包 “1”。
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