公开(公告)号：US5465380A

公开(公告)日：1995-11-07

申请号：US222949

申请日：1994-04-04

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F9/00

CPC分类号： G06F9/54 ,  G06F15/161

摘要： A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

摘要翻译： 一种并行处理器系统，其包括多个处理器，每个处理器用于执行多个相互关联的程序和传送电路中的至少一个。 传送电路连接到处理器，并且被提供用于将由任何一个处理器执行一个程序期间的任何一个程序输出的数据传送到分配了接收程序的其他处理器。 响应于由一个处理器执行一个程序期间输出的节目识别码来执行传送操作以识别接收节目。

公开(公告)号：US5301322A

公开(公告)日：1994-04-05

申请号：US912215

申请日：1992-07-10

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F9/00

CPC分类号： G06F9/54 ,  G06F15/161

摘要： A parallel processor system includes a transfer circuit and a plurality of processors each of which executes at least one of a plurality of mutually associated programs. The transfer circuit transfers data from a sending program allotted to one processor to a receiving program allotted to another processor by identifying the other processor and the receiving program based on a job number and within-job process number outputted by the sending program.

摘要翻译： 并行处理器系统包括传送电路和多个处理器，每个处理器执行多个相互关联的程序中的至少一个。 传送电路根据发送程序输出的作业号和作业内编号，通过识别其他处理器和接收程序，将数据从分配给一个处理器的发送程序传送到分配给另一个处理器的接收程序。

公开(公告)号：US5010477A

公开(公告)日：1991-04-23

申请号：US109293

申请日：1987-10-15

申请人： Koichiro Omoda ,  Teruo Tanaka ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Nagashima

发明人： Koichiro Omoda ,  Teruo Tanaka ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Nagashima

IPC分类号： G06F15/80

CPC分类号： G06F15/8092 ,  G06F15/8015

摘要： A parallel processor system having a plurality of processor elements includes transfer information generation circuit for generating transfer information by adding to vector data a data identifier for the vector data and a destination processor element number, transmission circuit for sending the transfer information to a data communication path, receive circuit for holding the transfer information sent from the data communication path, and vector register for continuously reading related element data from the receive circuit based on the data identifiers generated by the transfer information generation circuit.

摘要翻译： 具有多个处理器单元的并行处理器系统包括：传送信息生成电路，用于通过向矢量数据添加用于矢量数据的数据标识符和目的处理器单元号来生成传送信息，发送电路，用于将传送信息发送到数据通信路径 ，用于保持从数据通信路径发送的传送信息的接收电路，以及用于基于由传送信息生成电路产生的数据标识符从接收电路连续读取相关元素数据的向量寄存器。

公开(公告)号：US5113390A

公开(公告)日：1992-05-12

申请号：US508065

申请日：1990-04-10

申请人： Takehisa Hayashi ,  Koichiro Omoda ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

发明人： Takehisa Hayashi ,  Koichiro Omoda ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

IPC分类号： H04L12/935 ,  H04L12/937

CPC分类号： H04L49/3018 ,  H04L49/254 ,  H04L49/3027

摘要： A computer system having a plurality of processors assigned first and second address portions are connected to a plurality of switch circuits. A first group transfer networks are connected to a corresponding first group of the plurality of switch circuits. Each of the transfer networks concurrently transfer data among the switch circuits. The switch circuits are provided to processors of a first kind arranged in a plurality of processor groups. The processor groups of the first kind include processors with different values for first address portions and the same value for second address portions. Additional transfer networks, processors and switches functioning in a similar manner are provided to expand the above system. In another embodiment of the present invention a data transfer network is provided having a plurality of processors for data transfer. The network includes a plurality of multistage switches each belonging to one of plural stages and connected to the switches of a preceding stage and to switches of the succeeding stage. Each of the switches are arranged to receive packets from a preceding switch. A packet includes a target process address and data to be transferred. A path select device is connected to receive packets and is also connected to plural switches belonging to a next stage for the transfer of the received partial addresses and partial data. A control device is connected to receive the partial addresses and partial data and is responsive to a predetermined bit within the received partial addresses. The control means is responsive to the arrival of the first partial address of the packet.

公开(公告)号：US4985827A

公开(公告)日：1991-01-15

申请号：US226376

申请日：1988-07-29

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Junji Nakagoshi ,  Kazuo Ojima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Junji Nakagoshi ,  Kazuo Ojima

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F15/80

CPC分类号： G06F15/8092 ,  G06F15/8084

摘要： A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

公开(公告)号：US5867679A

公开(公告)日：1999-02-02

申请号：US647773

申请日：1991-01-30

申请人： Teruo Tanaka ,  Naoki Hamanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Junji Nakagoshi ,  Kazuo Ojima

发明人： Teruo Tanaka ,  Naoki Hamanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Junji Nakagoshi ,  Kazuo Ojima

IPC分类号： G06F9/44 ,  G06F15/17 ,  G06F15/80 ,  G06F15/82

CPC分类号： G06F15/8015 ,  G06F9/4494 ,  G06F15/17

摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.

摘要翻译： 并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。 数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。 提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。

公开(公告)号：US5086498A

公开(公告)日：1992-02-04

申请号：US145614

申请日：1988-01-10

申请人： Teruo Tanaka ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Teruo Tanaka ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F15/8092 ,  G06F15/17 ,  G06F15/173

摘要： In a multiprocessor digital computer system ID data, coupled with data for which inter-processor communication is desired, is communicated from one processor and held temporarily with data in a receiver buffer (associative memory) in a receiving processor. This ID is divided into main ID data MK and sub ID data SK. Main ID data MK is used for searching data from a receive buffer. The sub ID data SK are used as an ID of the data in the receive processor.

摘要翻译： 在多处理器数字计算机系统ID数据中，与期望的处理器间通信的数据相耦合，从一个处理器传送并暂时保存在接收处理器中的接收缓冲器（关联存储器）中的数据。 该ID被划分为主ID数据MK和子ID数据SK。 主ID数据MK用于从接收缓冲器搜索数据。 子ID数据SK用作接收处理器中的数据的ID。

公开(公告)号：US5043873A

公开(公告)日：1991-08-27

申请号：US395444

申请日：1989-08-17

申请人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

发明人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

IPC分类号： G06F9/45 ,  G06F9/50

CPC分类号： G06F9/5016 ,  G06F8/451 ,  G06F2209/484

摘要： A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data. Concurrently and in parallel with the execution of the task program, the data is transmitted to each of the elemental processors that are awaiting the data with only a write instruction and without any communications instruction.

公开(公告)号：US4951193A

公开(公告)日：1990-08-21

申请号：US85646

申请日：1987-08-14

申请人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

发明人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

IPC分类号： G06F9/45 ,  G06F9/50

CPC分类号： G06F9/5016 ,  G06F8/451 ,  G06F2209/484

摘要： In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

摘要翻译： 在访问存储器时，每个元件处理器执行构造成为每个元件处理器指定属于预定本地地址区域的地址的程序。 当由元件处理器执行存储器写入指令时，检测由指令指定的存储器地址是否与预定地址一致。 如果检测到，则属于另一元件处理器的本地地址空间并分配给首先提到的预定地址的预定地址以及响应写指令写入的数据被发送到另一元件处理器以指示数据为 在其中写入作为复制数据。 对于每个元件处理器独立地确定要执行的下一个任务。

公开(公告)号：US4918686A

公开(公告)日：1990-04-17

申请号：US224894

申请日：1988-07-27

申请人： Takehisa Hayashi ,  Koichiro Omada ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

发明人： Takehisa Hayashi ,  Koichiro Omada ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

IPC分类号： H04L12/935 ,  H04L12/937

CPC分类号： H04L49/3018 ,  H04L49/254 ,  H04L49/3027

摘要： In a data transfer network of the present invention, each switch is designed such that when the partial address necessary for a given switch to determine another switch belonging to the succeeding stage, to which a packet is to be delivered from the given switch, is included in the first one of plural subpackets supplied to the given switch and each having the partial address, the given switch starts its switching operation upon arrival of the first subpacket. In a preferred embodiment, when the partial address necessary for the succeeding switch to make its switching operation is not included in the first subpacket, the partial addresses are exchanged between the subpackets by the preceding switch so that the said partial address is now included in the first subpacket.

摘要翻译： 在本发明的数据传输网络中，每个交换机被设计成使得当给定交换机所需的部分地址被确定为属于后一级的另一交换机时，包括从给定交换机向其传送分组的部分地址 在提供给给定开关并且每个具有部分地址的多个子分组中的第一个子分组中，给定开关在第一子分组到达时开始其切换操作。 在优选实施例中，当后续交换机进行其切换操作所需的部分地址不包括在第一子分组中时，通过前一交换机在子分组之间交换部分地址，使得所述部分地址现在包括在 第一个子分组