公开(公告)号：US20060288348A1

公开(公告)日：2006-12-21

申请号：US11485273

申请日：2006-07-13

申请人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

发明人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

IPC分类号： G06F9/46

CPC分类号： G06F9/5077 ,  G06F9/5083

摘要： Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the allocation rations of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

公开(公告)号：US06757788B2

公开(公告)日：2004-06-29

申请号：US09941834

申请日：2001-08-30

申请人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Hiromitsu Maeda ,  Naoki Hamanaka

发明人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Hiromitsu Maeda ,  Naoki Hamanaka

IPC分类号： G06F1300

CPC分类号： G06F12/0817 ,  G06F12/0815

摘要： A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

摘要翻译： 一种用于具有由网络互连的多个CPU节点，存储器节点和I / O节点的多CPU系统的高速缓存一致性控制系统。 每个CPU节点控制电路具有访问权限存储器，用于以比CPU的内部高速缓存的块大小更大的扩展节点来管理节点的访问权限。 当执行存储器访问时，参考访问权限存储器，并且如果节点对包括目标块的扩展块具有访问权限，则在其他节点处访问该块而不进行高速缓存一致性控制。

公开(公告)号：US06728258B1

公开(公告)日：2004-04-27

申请号：US09456383

申请日：1999-12-08

申请人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

发明人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

IPC分类号： H04L1266

CPC分类号： G06F15/17375 ,  G06F12/0833 ,  G06F2212/1016 ,  G06F2212/206

摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

摘要翻译： 在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路 请求以下列方式。 对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。 对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。 对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

公开(公告)号：US6011791A

公开(公告)日：2000-01-04

申请号：US747344

申请日：1996-11-12

申请人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

发明人： Tetsuhiko Okada ,  Naoki Hamanaka ,  Naohiko Irie ,  Takehisa Hayashi ,  Tetsuya Mochida ,  Masabumi Shibata ,  Youichi Tanaka ,  Yasuhiro Ishii

IPC分类号： G06F15/173 ,  G06F13/38 ,  H04L12/56

CPC分类号： G06F15/17375

摘要： In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

摘要翻译： 在通过具有多个端口的交叉开关连接到处理器单元，存储器单元和连接到输入/输出设备的输入/输出单元的多处理器系统中，每个处理器单元的发射器具有用于确定接入的目的地的电路 请求以下列方式。 对于对主存储器的访问请求，访问请求被传送到存储要访问的数据的所有处理器单元和一个存储单元。 对于对输入/输出设备的存储器映射寄存器的访问请求，将访问请求广播到所有输入/输出单元。 对于属于处理器单元，存储器单元和输入/输出单元中的任何一个的存储器映射寄存器的访问请求，访问请求经由交叉开关广播到所有单元。

公开(公告)号：US5742766A

公开(公告)日：1998-04-21

申请号：US34805

申请日：1993-03-19

申请人： Shigeo Takeuchi ,  Hideo Wada ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Teruo Tanaka ,  Yasuhiro Ogata ,  Taturu Toba ,  Mitsuyoshi Igai

发明人： Shigeo Takeuchi ,  Hideo Wada ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Teruo Tanaka ,  Yasuhiro Ogata ,  Taturu Toba ,  Mitsuyoshi Igai

IPC分类号： G06F9/52 ,  G06F15/173 ,  G06F15/80 ,  G06F13/12

CPC分类号： G06F15/17343 ,  G06F15/17381

摘要： An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.

摘要翻译： 来自每个处理器的操作完成信号和收敛结果信号被传送到X方向互连开关，并且这些信号的AND在每个互连开关中以开关单元获得，该信号被发送到所有Y方向互连开关，通过 每个继电器开关中的同步信号继电器开关等，在互连开关中的每个开关单元中获得这些信号的AND，并且其结果通过每个同步信号继电器开关传送到每个处理器。 由此，来自所有处理器的操作完成信号和收敛结果信号的逻辑积的逻辑积并行发送到所有处理器。

公开(公告)号：US5465380A

公开(公告)日：1995-11-07

申请号：US222949

申请日：1994-04-04

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F9/00

CPC分类号： G06F9/54 ,  G06F15/161

摘要： A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

摘要翻译： 一种并行处理器系统，其包括多个处理器，每个处理器用于执行多个相互关联的程序和传送电路中的至少一个。 传送电路连接到处理器，并且被提供用于将由任何一个处理器执行一个程序期间的任何一个程序输出的数据传送到分配了接收程序的其他处理器。 响应于由一个处理器执行一个程序期间输出的节目识别码来执行传送操作以识别接收节目。

公开(公告)号：US5377333A

公开(公告)日：1994-12-27

申请号：US945483

申请日：1992-09-15

申请人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

发明人： Junji Nakagoshi ,  Naoki Hamanaka ,  Hiroyuki Chiba ,  Tatsuo Higuchi ,  Shinichi Shutoh ,  Yasuhiro Ogata ,  Shigeo Takeuchi ,  Tatsuru Toba

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17375

摘要： Crossbar switches having 2.sup.n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2.sup.n processors. Auxiliary processors that perform parallel processing administrative functions and input/output functions are arranged at the remainder ports of the crossbar switches. Exchangers are provided to connect each processor and its crossbar switches. Parallel processing may be executed by the 2.sup.n processors independently of processing by the auxiliary processors for speed. One mounting unit is formed of a crossbar switch of one dimension, the processor group connected to that crossbar switch, and all of the crossbar switches of a different dimension that are connected to one of the processors of the one processor group. The parallel processor system is mounted by just combining mounting units with no need for special LSIs or frames or the like on which to mount the crossbar switches and without the interfaces that connect the processor and the network becoming concentrated in one place.

摘要翻译： 具有2n + 1个端口和计算集群的交叉开关被布置成使得每个交叉开关连接到2n个处理器。 执行并行处理管理功能和输入/输出功能的辅助处理器被布置在交叉开关的其余端口处。 提供交换器来连接每个处理器及其交叉开关。 独立于辅助处理器对速度的处理，可以由2n个处理器执行并行处理。 一个安装单元由一维的交叉开关构成，处理器组连接到该交叉开关，以及连接到一个处理器组的一个处理器的不同维度的所有交叉开关。 并行处理器系统仅通过组合安装单元来安装，不需要特殊的LSI或框架等，在其上安装交叉开关，并且没有连接处理器和网络的接口变得集中在一个地方。

公开(公告)号：US5043873A

公开(公告)日：1991-08-27

申请号：US395444

申请日：1989-08-17

申请人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

发明人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

IPC分类号： G06F9/45 ,  G06F9/50

CPC分类号： G06F9/5016 ,  G06F8/451 ,  G06F2209/484

摘要： A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data. Concurrently and in parallel with the execution of the task program, the data is transmitted to each of the elemental processors that are awaiting the data with only a write instruction and without any communications instruction.

公开(公告)号：US4951193A

公开(公告)日：1990-08-21

申请号：US85646

申请日：1987-08-14

申请人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

发明人： Akira Muramatsu ,  Kousuke Sakoda ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Makoto Nohmi ,  Naoki Hamanaka ,  Shigeo Nagashima ,  Teruo Tanaka

IPC分类号： G06F9/45 ,  G06F9/50

CPC分类号： G06F9/5016 ,  G06F8/451 ,  G06F2209/484

摘要： In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

摘要翻译： 在访问存储器时，每个元件处理器执行构造成为每个元件处理器指定属于预定本地地址区域的地址的程序。 当由元件处理器执行存储器写入指令时，检测由指令指定的存储器地址是否与预定地址一致。 如果检测到，则属于另一元件处理器的本地地址空间并分配给首先提到的预定地址的预定地址以及响应写指令写入的数据被发送到另一元件处理器以指示数据为 在其中写入作为复制数据。 对于每个元件处理器独立地确定要执行的下一个任务。

公开(公告)号：US08397239B2

公开(公告)日：2013-03-12

申请号：US12962537

申请日：2010-12-07

申请人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

发明人： Shinichi Kawamoto ,  Tatsuo Higuchi ,  Naoki Hamanaka

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F15/173 ,  G06F15/177

CPC分类号： G06F9/5077 ,  G06F9/5083

摘要： Disclosed are a virtual computer system and method, wherein computer resources are automatically and optimally allocated to logical partitions according to loads to be accomplished by operating systems in the logical partitions and setting information based on a knowledge of workloads that run on the operating systems. Load measuring modules are installed on the operating systems in order to measure the loads to be accomplished by the operating systems. A manager designates the knowledge concerning the workloads on the operating systems through a user interface. An adaptive control module determines the allocation rations of the computer resources relative to the logical partitions according to the loads and the settings, and issues an allocation varying instruction to a hypervisor so as to thus instruct variation of allocations.

摘要翻译： 公开了一种虚拟计算机系统和方法，其中计算机资源根据要由逻辑分区中的操作系统完成的负载自动和最佳地分配给逻辑分区，并且基于在操作系统上运行的工作负载的知识来设置信息。 负载测量模块安装在操作系统上，以便测量操作系统要完成的负载。 经理通过用户界面指定关于操作系统的工作负载的知识。 自适应控制模块根据负载和设置确定计算机资源相对于逻辑分区的分配比例，并向管理程序发出分配变化指令，从而指示分配的变化。