公开(公告)号：US20130222042A1

公开(公告)日：2013-08-29

申请号：US13780780

申请日：2013-02-28

申请人： Naoto KIKUCHI ,  Kenichi TAKAGI

发明人： Naoto KIKUCHI ,  Kenichi TAKAGI

IPC分类号： H03K17/04

CPC分类号： H03K17/04 ,  H03K17/04123

摘要： A drive circuit is provided with a charge pump including a capacitor. The capacitor of the charge pump is configured to be charged in the first stage and to be connected with the gate terminal of the switching device in the second stage. The charge pump is configured to be able to adjust a charging voltage charged in the capacitor according to an order signal.

摘要翻译： 驱动电路设置有包括电容器的电荷泵。 电荷泵的电容器被配置为在第一级中被充电并且在第二级中与开关装置的栅极端子连接。 电荷泵被配置为能够根据订单信号调整充电在电容器中的充电电压。

公开(公告)号：US20110093753A1

公开(公告)日：2011-04-21

申请号：US12907563

申请日：2010-10-19

申请人： Kenichi TAKAGI

发明人： Kenichi TAKAGI

IPC分类号： G06F11/10 ,  H03L7/06 ,  G06F11/07

CPC分类号： H03L7/0814 ,  G06F11/1004 ,  G06F2213/0038 ,  H03L7/087

摘要： Provided is a phase calibration circuit to suppress degradation of transfer efficiency when reading data from a memory card. The phase calibration circuit includes a receive clock generator that generates clock signals including a first clock signal (FCS) with a phase shifted with respect to a base clock signal, a second clock signal with a phase advanced with respect to the FCS, and a third clock signal with a phase delayed with respect to the FCS; a determination unit that acquires data blocks, each of which including a data body and detection information for detecting an error, in accordance with the clock signals, determines whether an error occurs by using the detection information of the data blocks, and outputs determination results; and a phase adjustment unit that instructs the receive clock generator to adjust a phase of the FCS depending on the determination results.

摘要翻译： 提供了一种相位校准电路，用于在从存储卡读取数据时抑制转印效率的劣化。 相位校准电路包括接收时钟发生器，其产生包括相对于基本时钟信号相移的第一时钟信号（FCS）的时钟信号，具有相对于FCS前进的相位的第二时钟信号，以及第三时钟信号 具有相对于FCS相位延迟的时钟信号; 确定单元，其根据时钟信号获取数据块，每个数据块包括数据体和用于检测错误的检测信息，通过使用数据块的检测信息来确定是否发生错误，并输出确定结果; 以及相位调整单元，其指示接收时钟发生器根据确定结果来调整FCS的相位。